SRAM_CTRL/MAIN Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.370m 793.823us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.720s 24.447us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 11.887us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.330s 831.383us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.720s 15.446us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.620s 5.836ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 11.887us 20 20 100.00
sram_ctrl_csr_aliasing 0.720s 15.446us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 5.435m 21.308ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.670m 36.253ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 28.521m 27.468ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.104m 8.156ms 50 50 100.00
V2 bijection sram_ctrl_bijection 47.729m 351.685ms 49 50 98.00
V2 access_during_key_req sram_ctrl_access_during_key_req 31.670m 20.893ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.177m 36.068ms 50 50 100.00
V2 executable sram_ctrl_executable 38.287m 186.964ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.333m 3.449ms 50 50 100.00
sram_ctrl_partial_access_b2b 8.885m 98.480ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.654m 1.324ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.442m 3.131ms 50 50 100.00
V2 regwen sram_ctrl_regwen 35.657m 17.427ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 3.950s 2.404ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.257h 116.798ms 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.750s 56.845us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.700s 538.601us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.700s 538.601us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.720s 24.447us 5 5 100.00
sram_ctrl_csr_rw 0.720s 11.887us 20 20 100.00
sram_ctrl_csr_aliasing 0.720s 15.446us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.880s 136.327us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.720s 24.447us 5 5 100.00
sram_ctrl_csr_rw 0.720s 11.887us 20 20 100.00
sram_ctrl_csr_aliasing 0.720s 15.446us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.880s 136.327us 20 20 100.00
V2 TOTAL 738 740 99.73
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.211m 100.769ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 2.200s 860.588us 5 5 100.00
sram_ctrl_tl_intg_err 3.000s 2.685ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 2.200s 860.588us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.000s 2.685ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 35.657m 17.427ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 11.887us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 38.287m 186.964ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 38.287m 186.964ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 38.287m 186.964ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.177m 36.068ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.211m 100.769ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.370m 793.823us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.370m 793.823us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 38.287m 186.964ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 2.200s 860.588us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.177m 36.068ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 2.200s 860.588us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 2.200s 860.588us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.370m 793.823us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 2.200s 860.588us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.825m 3.661ms 48 50 96.00
V3 TOTAL 48 50 96.00
TOTAL 1036 1040 99.62

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52

Failure Buckets

Past Results