SRAM_CTRL/MAIN Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.310m	479.383us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	47.630us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	31.046us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.150s	295.022us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	138.771us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.530s	1.402ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	31.046us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	138.771us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.270m	229.332ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.680m	4.379ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	32.333m	22.389ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.870m	27.187ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	44.909m	165.581ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	33.818m	237.181ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.743m	18.547ms	50	50	100.00
V2	executable	sram_ctrl_executable	27.670m	9.919ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.519m	2.197ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.814m	109.745ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.290m	815.304us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.986m	3.128ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	27.611m	5.154ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.430s	3.350ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.372h	426.563ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.710s	13.683us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.130s	297.184us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.130s	297.184us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	47.630us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	31.046us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	138.771us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	48.166us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	47.630us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	31.046us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	138.771us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	48.166us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.081m	50.271ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.610s	1.675ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.530s	2.325ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.610s	1.675ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.530s	2.325ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	27.611m	5.154ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	31.046us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	27.670m	9.919ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	27.670m	9.919ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	27.670m	9.919ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.743m	18.547ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.081m	50.271ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.310m	479.383us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.310m	479.383us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	27.670m	9.919ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.610s	1.675ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.743m	18.547ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.610s	1.675ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.610s	1.675ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.310m	479.383us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.610s	1.675ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.332m	1.436ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1038	1040	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	96.99	100.00	100.00	98.60	99.70	98.52

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_multiple_keys has 1 failures.

    • 9.sram_ctrl_multiple_keys.46568652287454225592951563051975203746571435333722014762563107036559789542071
      Line 300, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 152877150702 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x27a6949b
        UVM_INFO @ 152877150702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 40.sram_ctrl_stress_all.89347338898465993334985294191116879381148276873513994553169854246639510012274
      Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 20990368385 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x4f9d183a
        UVM_INFO @ 20990368385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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