SRAM_CTRL/MAIN Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.391m 1.319ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.720s 24.261us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.680s 14.506us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.250s 176.610us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.750s 83.536us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.720s 389.821us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.680s 14.506us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 83.536us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 5.710m 86.086ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.589m 5.139ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 29.616m 88.630ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.986m 25.117ms 50 50 100.00
V2 bijection sram_ctrl_bijection 44.122m 606.715ms 49 50 98.00
V2 access_during_key_req sram_ctrl_access_during_key_req 29.971m 255.925ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.812m 17.067ms 50 50 100.00
V2 executable sram_ctrl_executable 27.754m 92.189ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.667m 1.758ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.986m 30.944ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.448m 800.297us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.826m 1.650ms 50 50 100.00
V2 regwen sram_ctrl_regwen 28.787m 67.602ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 5.260s 6.692ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.361h 94.620ms 47 50 94.00
V2 alert_test sram_ctrl_alert_test 0.720s 22.160us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.990s 158.814us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.990s 158.814us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.720s 24.261us 5 5 100.00
sram_ctrl_csr_rw 0.680s 14.506us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 83.536us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.800s 83.228us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.720s 24.261us 5 5 100.00
sram_ctrl_csr_rw 0.680s 14.506us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 83.536us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.800s 83.228us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 56.510s 14.393ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 5.990s 1.375ms 5 5 100.00
sram_ctrl_tl_intg_err 4.300s 7.579ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 5.990s 1.375ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 4.300s 7.579ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 28.787m 67.602ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.680s 14.506us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 27.754m 92.189ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 27.754m 92.189ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 27.754m 92.189ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.812m 17.067ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 56.510s 14.393ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.391m 1.319ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.391m 1.319ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 27.754m 92.189ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 5.990s 1.375ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.812m 17.067ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 5.990s 1.375ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 5.990s 1.375ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.391m 1.319ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 5.990s 1.375ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 5.762m 11.148ms 48 50 96.00
V3 TOTAL 48 50 96.00
TOTAL 1033 1040 99.33

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.06 99.81 96.99 100.00 100.00 98.60 99.70 98.33

Failure Buckets

Past Results