SRAM_CTRL/MAIN Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.049m	5.642ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.680s	56.470us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	28.533us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.300s	343.353us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	69.109us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.040s	549.557us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	28.533us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	69.109us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.312m	275.321ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.472m	39.550ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	38.319m	30.850ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.846m	19.163ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	47.708m	718.585ms	47	50	94.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	26.579m	16.756ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.781m	63.517ms	50	50	100.00
V2	executable	sram_ctrl_executable	28.245m	15.982ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.035m	1.343ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.345m	29.483ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.436m	6.953ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.432m	1.601ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	26.893m	23.069ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.040s	5.557ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.821h	2.038s	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.730s	66.608us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.730s	146.851us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.730s	146.851us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.680s	56.470us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	28.533us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	69.109us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	40.755us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.680s	56.470us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	28.533us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	69.109us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	40.755us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.429m	141.100ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.560s	743.120us	5	5	100.00
		sram_ctrl_tl_intg_err	2.770s	452.131us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.560s	743.120us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.770s	452.131us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	26.893m	23.069ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	28.533us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	28.245m	15.982ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	28.245m	15.982ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	28.245m	15.982ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.781m	63.517ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.429m	141.100ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.049m	5.642ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.049m	5.642ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	28.245m	15.982ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.560s	743.120us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.781m	63.517ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.560s	743.120us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.560s	743.120us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.049m	5.642ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.560s	743.120us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.299m	1.685ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	96.99	100.00	100.00	98.60	99.70	98.52

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

  • Test sram_ctrl_bijection has 3 failures.

    • 3.sram_ctrl_bijection.111889603863943617953907166974260133828382551781540394182440756178602731352815
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.sram_ctrl_bijection.4608864883599700525494688256161298832026434007164196007482634275992929864165
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 13.sram_ctrl_stress_all.46619701397335779140270399069825237136098969776074176546473316954168178091371
      Line 290, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 107570224696 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xd3445897
        UVM_INFO @ 107570224696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 32.sram_ctrl_stress_all_with_rand_reset.22904948309253739666885076704694307208971087190190294855565501508865150993161
      Line 283, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4753488029 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4753488029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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