SRAM_CTRL/MAIN Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: 18c8953cf1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.448m 919.677us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.670s 35.451us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 46.800us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.130s 117.604us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.830s 37.613us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.720s 3.418ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 46.800us 20 20 100.00
sram_ctrl_csr_aliasing 0.830s 37.613us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.018m 162.997ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.687m 19.524ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 26.021m 41.171ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 8.417m 8.703ms 50 50 100.00
V2 bijection sram_ctrl_bijection 46.669m 920.064ms 48 50 96.00
V2 access_during_key_req sram_ctrl_access_during_key_req 27.925m 83.272ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.301m 193.056ms 50 50 100.00
V2 executable sram_ctrl_executable 38.911m 109.022ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.727m 1.061ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.627m 28.106ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.807m 1.559ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.721m 3.129ms 50 50 100.00
V2 regwen sram_ctrl_regwen 32.634m 18.672ms 48 50 96.00
V2 ram_cfg sram_ctrl_ram_cfg 4.710s 4.196ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.434h 263.164ms 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.730s 11.677us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.230s 191.635us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.230s 191.635us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.670s 35.451us 5 5 100.00
sram_ctrl_csr_rw 0.720s 46.800us 20 20 100.00
sram_ctrl_csr_aliasing 0.830s 37.613us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.810s 59.532us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.670s 35.451us 5 5 100.00
sram_ctrl_csr_rw 0.720s 46.800us 20 20 100.00
sram_ctrl_csr_aliasing 0.830s 37.613us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.810s 59.532us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.203m 88.031ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.540s 1.622ms 5 5 100.00
sram_ctrl_tl_intg_err 2.990s 449.421us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.540s 1.622ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.990s 449.421us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 32.634m 18.672ms 48 50 96.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 46.800us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 38.911m 109.022ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 38.911m 109.022ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 38.911m 109.022ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.301m 193.056ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.203m 88.031ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.448m 919.677us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.448m 919.677us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 38.911m 109.022ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.540s 1.622ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.301m 193.056ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.540s 1.622ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.540s 1.622ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.448m 919.677us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.540s 1.622ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 2.654m 1.577ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1035 1040 99.52

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.06 99.81 96.99 100.00 100.00 98.60 99.70 98.33

Failure Buckets

Past Results