SRAM_CTRL/MAIN Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.894m 1.357ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.690s 14.102us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.800s 14.018us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.290s 238.068us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.730s 15.047us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.440s 6.838ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.800s 14.018us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 15.047us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 5.504m 86.055ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.691m 16.771ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 33.113m 22.029ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.085m 19.158ms 50 50 100.00
V2 bijection sram_ctrl_bijection 43.558m 115.056ms 49 50 98.00
V2 access_during_key_req sram_ctrl_access_during_key_req 34.208m 20.690ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.360m 132.031ms 50 50 100.00
V2 executable sram_ctrl_executable 33.471m 8.349ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 3.266m 546.090us 50 50 100.00
sram_ctrl_partial_access_b2b 12.935m 142.025ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.597m 6.952ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.964m 2.895ms 50 50 100.00
V2 regwen sram_ctrl_regwen 36.684m 196.930ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.480s 3.359ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.763h 417.072ms 48 50 96.00
V2 alert_test sram_ctrl_alert_test 0.730s 26.636us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 3.860s 363.063us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 3.860s 363.063us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.690s 14.102us 5 5 100.00
sram_ctrl_csr_rw 0.800s 14.018us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 15.047us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 29.041us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.690s 14.102us 5 5 100.00
sram_ctrl_csr_rw 0.800s 14.018us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 15.047us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 29.041us 20 20 100.00
V2 TOTAL 737 740 99.59
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.216m 64.040ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.330s 392.925us 5 5 100.00
sram_ctrl_tl_intg_err 3.040s 2.198ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.330s 392.925us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.040s 2.198ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 36.684m 196.930ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.800s 14.018us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 33.471m 8.349ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 33.471m 8.349ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 33.471m 8.349ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.360m 132.031ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.216m 64.040ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.894m 1.357ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.894m 1.357ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 33.471m 8.349ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.330s 392.925us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.360m 132.031ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.330s 392.925us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.330s 392.925us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.894m 1.357ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.330s 392.925us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 6.421m 8.119ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1037 1040 99.71

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52

Failure Buckets

Past Results