SRAM_CTRL/MAIN Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.764m	1.855ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	24.496us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	80.110us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.480s	1.384ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	17.976us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.650s	1.393ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	80.110us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	17.976us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.141m	206.671ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.666m	9.927ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	41.978m	27.297ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.361m	117.957ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	47.209m	634.780ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	34.762m	23.245ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.097m	72.210ms	50	50	100.00
V2	executable	sram_ctrl_executable	30.287m	90.832ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	3.394m	5.328ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.594m	59.732ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.503m	1.532ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.655m	1.568ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	37.622m	23.670ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.120s	5.576ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.853h	1.119s	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.720s	23.650us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.770s	557.593us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.770s	557.593us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	24.496us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	80.110us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	17.976us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	27.652us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	24.496us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	80.110us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	17.976us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	27.652us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.121m	117.180ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.230s	297.648us	5	5	100.00
		sram_ctrl_tl_intg_err	2.660s	284.151us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.230s	297.648us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.660s	284.151us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	37.622m	23.670ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	80.110us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.287m	90.832ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.287m	90.832ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.287m	90.832ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.097m	72.210ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.121m	117.180ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.764m	1.855ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.764m	1.855ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.287m	90.832ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.230s	297.648us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.097m	72.210ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.230s	297.648us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.230s	297.648us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.764m	1.855ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.230s	297.648us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.291m	25.940ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1038	1040	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	96.99	100.00	100.00	98.60	99.70	98.52

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 25.sram_ctrl_stress_all.3242896220660966226076438040424864931973262619673466330657697755305674856649
      Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 1368324457073 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x15c1e2e7
        UVM_INFO @ 1368324457073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 27.sram_ctrl_stress_all.74246105626277505492301670875529210915872767983647272972948923724478539766210
      Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all/latest/run.log

        Job ID: smart:3b9800aa-cda4-467a-bfa0-95092cc8aee2
      

Past Results

• Latest
• 2024.05.10_04.45.37
• 2024.05.08_03.55.13
• 2024.05.06_05.10.20
• 2024.05.03_05.25.00
• 2024.05.01_04.39.10
• 2024.04.29_08.12.58
• 2024.04.26_08.04.54