SRAM_CTRL/MAIN Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.536m 779.421us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.750s 47.427us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.730s 18.138us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.680s 694.382us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.770s 17.431us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 6.270s 6.926ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.730s 18.138us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 17.431us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 5.602m 93.960ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.843m 45.284ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 33.158m 104.511ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.092m 12.990ms 50 50 100.00
V2 bijection sram_ctrl_bijection 48.260m 155.768ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 31.432m 97.016ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 3.396m 248.012ms 50 50 100.00
V2 executable sram_ctrl_executable 41.846m 13.178ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 3.100m 1.303ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.169m 270.163ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.863m 1.378ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.899m 3.148ms 50 50 100.00
V2 regwen sram_ctrl_regwen 29.046m 117.797ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.260s 6.744ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.804h 352.986ms 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.710s 90.864us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.140s 192.503us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.140s 192.503us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.750s 47.427us 5 5 100.00
sram_ctrl_csr_rw 0.730s 18.138us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 17.431us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 68.757us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.750s 47.427us 5 5 100.00
sram_ctrl_csr_rw 0.730s 18.138us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 17.431us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 68.757us 20 20 100.00
V2 TOTAL 738 740 99.73
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 57.810s 29.436ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.930s 581.311us 5 5 100.00
sram_ctrl_tl_intg_err 3.040s 445.422us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.930s 581.311us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.040s 445.422us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 29.046m 117.797ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.730s 18.138us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 41.846m 13.178ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 41.846m 13.178ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 41.846m 13.178ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 3.396m 248.012ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 57.810s 29.436ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.536m 779.421us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.536m 779.421us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 41.846m 13.178ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.930s 581.311us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 3.396m 248.012ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.930s 581.311us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.930s 581.311us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.536m 779.421us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.930s 581.311us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 7.087m 3.253ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1038 1040 99.81

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52

Failure Buckets

Past Results