SRAM_CTRL/MAIN Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.801m	5.087ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	25.179us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.760s	92.082us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.190s	712.296us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	18.526us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.960s	3.542ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.760s	92.082us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	18.526us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.417m	43.114ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.996m	72.370ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	36.059m	21.192ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.522m	6.768ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	49.476m	689.624ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	33.917m	16.728ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.927m	78.161ms	50	50	100.00
V2	executable	sram_ctrl_executable	30.576m	184.543ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.643m	2.688ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.940m	33.632ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.828m	776.040us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.722m	809.874us	50	50	100.00
V2	regwen	sram_ctrl_regwen	36.265m	61.002ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.650s	1.343ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.260h	202.272ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.740s	47.604us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.990s	269.447us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.990s	269.447us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	25.179us	5	5	100.00
		sram_ctrl_csr_rw	0.760s	92.082us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	18.526us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	51.084us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	25.179us	5	5	100.00
		sram_ctrl_csr_rw	0.760s	92.082us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	18.526us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	51.084us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	57.200s	100.772ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.340s	297.670us	5	5	100.00
		sram_ctrl_tl_intg_err	3.180s	730.216us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.340s	297.670us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.180s	730.216us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	36.265m	61.002ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.760s	92.082us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.576m	184.543ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.576m	184.543ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.576m	184.543ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.927m	78.161ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	57.200s	100.772ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.801m	5.087ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.801m	5.087ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.576m	184.543ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.340s	297.670us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.927m	78.161ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.340s	297.670us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.340s	297.670us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.801m	5.087ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.340s	297.670us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.436m	3.828ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1036	1040	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	96.99	100.00	100.00	98.60	99.70	98.52

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 8.sram_ctrl_stress_all.35776236936553466586352011951901845137077635534358342522006015361383079154042
      Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 94434544651 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x9bd7bb50
        UVM_INFO @ 94434544651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test sram_ctrl_multiple_keys has 1 failures.

    • 23.sram_ctrl_multiple_keys.37080997117799295301767036180453911717080808565895066395222263574003772180619
      Line 298, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 150429776197 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x3c1b69a8
        UVM_INFO @ 150429776197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_executable has 1 failures.

    • 9.sram_ctrl_executable.56584150105000135844183132012605636160322977148738167812507892162708911559167
      Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 39964411412 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x45a44b09
        UVM_INFO @ 39964411412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 14.sram_ctrl_stress_all.63224186091903091215601252334331706358880016797310151694757298538396982763555
      Line 338, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 152758436314 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xdd9363c
        UVM_INFO @ 152758436314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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