SRAM_CTRL/MAIN Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: `eb776817a5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.095m	3.218ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	18.520us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	15.511us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.110s	237.070us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	19.157us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.650s	1.530ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	15.511us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	19.157us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.419m	229.340ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.721m	34.948ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	31.384m	27.946ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.363m	24.001ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	44.029m	634.450ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	29.885m	34.627ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.123m	240.764ms	50	50	100.00
V2	executable	sram_ctrl_executable	33.932m	48.463ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.756m	1.367ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.271m	97.756ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.786m	798.429us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.736m	3.130ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	32.576m	108.573ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.760s	4.814ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.346h	369.880ms	47	50	94.00
V2	alert_test	sram_ctrl_alert_test	0.720s	23.989us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.480s	116.691us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.480s	116.691us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	18.520us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	15.511us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	19.157us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	83.629us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	18.520us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	15.511us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	19.157us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	83.629us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	58.780s	100.641ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.080s	255.863us	5	5	100.00
		sram_ctrl_tl_intg_err	2.630s	1.027ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.080s	255.863us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.630s	1.027ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	32.576m	108.573ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	15.511us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	33.932m	48.463ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	33.932m	48.463ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	33.932m	48.463ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.123m	240.764ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	58.780s	100.641ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.095m	3.218ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.095m	3.218ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	33.932m	48.463ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.080s	255.863us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.123m	240.764ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.080s	255.863us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.080s	255.863us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.095m	3.218ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.080s	255.863us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.987m	7.428ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1034	1040	99.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	96.99	100.00	100.00	98.60	99.70	98.52

Failure Buckets

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

1.sram_ctrl_stress_all.58903453175637810182753224076737328847945168345688974324279980783314024244385
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 4137938022 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 4137938022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.sram_ctrl_stress_all.64463448439298312416146844459582390105831586677449546944772317584814310518413
Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 501550166 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 501550166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 4.sram_ctrl_stress_all_with_rand_reset.5793780914287688305160875693578546467427488258093657195632455497149359294442
    Line 322, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9039309101 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9039309101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 12.sram_ctrl_stress_all.96744804546510622874448687796063126729955799387122051973707342778333111015620
    Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 94132464793 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x2dd78b7c
  UVM_INFO @ 94132464793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 27.sram_ctrl_multiple_keys.38858947313939086395239812669325241887350149699146656217702199281461674006846
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 16644942666 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x2df4e994
  UVM_INFO @ 16644942666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 44.sram_ctrl_regwen.77401459102474092644570487028170573870575140855636950015218367055528659948645
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 15545288170 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x1758d86f
  UVM_INFO @ 15545288170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```