SRAM_CTRL/MAIN Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.716m	1.854ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	33.028us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	19.748us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.810s	50.290us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	70.281us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.580s	980.396us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	19.748us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	70.281us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.388m	42.985ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.671m	9.002ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	34.654m	23.591ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.917m	22.774ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	46.731m	501.600ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	37.528m	21.040ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.647m	213.710ms	50	50	100.00
V2	executable	sram_ctrl_executable	32.824m	72.891ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.944m	1.093ms	49	50	98.00
		sram_ctrl_partial_access_b2b	10.043m	210.834ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.673m	882.914us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.441m	12.942ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	34.324m	128.755ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.620s	6.673ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.773h	582.219ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.740s	20.466us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.600s	139.981us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.600s	139.981us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	33.028us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	19.748us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	70.281us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.790s	30.886us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	33.028us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	19.748us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	70.281us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.790s	30.886us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.075m	46.993ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.310s	1.524ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.360s	705.444us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.310s	1.524ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.360s	705.444us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	34.324m	128.755ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	19.748us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	32.824m	72.891ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	32.824m	72.891ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	32.824m	72.891ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.647m	213.710ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.075m	46.993ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.716m	1.854ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.716m	1.854ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	32.824m	72.891ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.310s	1.524ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.647m	213.710ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.310s	1.524ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.310s	1.524ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.716m	1.854ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.310s	1.524ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.775m	2.040ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	96.99	100.00	100.00	98.60	99.70	98.52

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:

  • Test sram_ctrl_multiple_keys has 1 failures.

    • 10.sram_ctrl_multiple_keys.67729522473071884021268936270930712724149845789916967446072310645044503531181
      Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 15510959354 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x35818c7d
        UVM_INFO @ 15510959354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 47.sram_ctrl_stress_all_with_rand_reset.105550042366090139924192266046126415439582012173486567727642999890884317884673
      Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 18576538217 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x2fee5ec3
        UVM_INFO @ 18576538217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 8.sram_ctrl_bijection.45195038161894957371846962604202974875587006846360834717529261970995099889738
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 29.sram_ctrl_stress_all_with_rand_reset.19718297068720152454813219733898262408309064365779620197213015204769345675699
      Line 291, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5393818359 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5393818359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_partial_access has 1 failures.

    • 38.sram_ctrl_partial_access.104367531903782643640388892214342281823235659520407851657583284535231192630323
      Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access/latest/run.log

        UVM_FATAL @ 15545412423 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x315339d
        UVM_INFO @ 15545412423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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