SRAM_CTRL/MAIN Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.775m 1.792ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.720s 32.228us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.700s 20.667us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.260s 178.882us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 58.624us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.760s 760.745us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.700s 20.667us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 58.624us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 5.733m 86.105ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.955m 48.817ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 29.305m 49.299ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.320m 6.096ms 50 50 100.00
V2 bijection sram_ctrl_bijection 45.010m 150.992ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 37.011m 33.093ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.087m 232.405ms 50 50 100.00
V2 executable sram_ctrl_executable 34.742m 13.761ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.544m 853.943us 50 50 100.00
sram_ctrl_partial_access_b2b 11.256m 114.104ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.546m 775.232us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.723m 1.596ms 50 50 100.00
V2 regwen sram_ctrl_regwen 27.800m 62.841ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.140s 5.593ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.322h 1.144s 50 50 100.00
V2 alert_test sram_ctrl_alert_test 0.710s 33.794us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.890s 161.880us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.890s 161.880us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.720s 32.228us 5 5 100.00
sram_ctrl_csr_rw 0.700s 20.667us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 58.624us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 94.315us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.720s 32.228us 5 5 100.00
sram_ctrl_csr_rw 0.700s 20.667us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 58.624us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 94.315us 20 20 100.00
V2 TOTAL 740 740 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 59.370s 29.391ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.170s 1.367ms 5 5 100.00
sram_ctrl_tl_intg_err 4.980s 3.782ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.170s 1.367ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 4.980s 3.782ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 27.800m 62.841ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.700s 20.667us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 34.742m 13.761ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 34.742m 13.761ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 34.742m 13.761ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.087m 232.405ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 59.370s 29.391ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.775m 1.792ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.775m 1.792ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 34.742m 13.761ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.170s 1.367ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.087m 232.405ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.170s 1.367ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.170s 1.367ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.775m 1.792ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.170s 1.367ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 6.977m 1.671ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1040 1040 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 16 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52

Past Results