SRAM_CTRL/MAIN Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.151m	14.341ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	113.096us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	41.957us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.340s	451.395us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	18.544us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.800s	752.921us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	41.957us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	18.544us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.293m	149.423ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.163m	21.606ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	40.720m	65.896ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.919m	9.438ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	57.514m	599.216ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.695m	4.751ms	3	50	6.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.500m	220.068ms	50	50	100.00
V2	executable	sram_ctrl_executable	29.689m	78.395ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	3.064m	6.847ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.168m	110.817ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.856m	1.112ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.926m	1.545ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	32.484m	66.016ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.830s	1.680ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.274h	1.045s	3	50	6.00
V2	alert_test	sram_ctrl_alert_test	0.710s	18.432us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.020s	615.729us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.020s	615.729us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	113.096us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	41.957us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	18.544us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	25.588us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	113.096us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	41.957us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	18.544us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	25.588us	20	20	100.00
V2		TOTAL			643	740	86.89
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.118m	63.999ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.290s	1.496ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.680s	679.507us	15	20	75.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.290s	1.496ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.680s	679.507us	15	20	75.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	32.484m	66.016ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	41.957us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.689m	78.395ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.689m	78.395ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.689m	78.395ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.500m	220.068ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.118m	63.999ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	3.151m	14.341ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.151m	14.341ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.151m	14.341ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.689m	78.395ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.290s	1.496ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.500m	220.068ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.290s	1.496ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.290s	1.496ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.151m	14.341ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.290s	1.496ms	5	5	100.00
V2S		TOTAL			40	45	88.89
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.925m	36.118ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			916	1040	88.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	11	68.75
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.32	99.43	95.61	100.00	100.00	96.55	99.56	97.07

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 72 failures:

Test sram_ctrl_stress_all has 47 failures.

0.sram_ctrl_stress_all.15367545088391535815037456600449415019055401968917870612804548639371273641264
Line 1015, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 18686142457 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 18686162659 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Update READBACK Value
  UVM_INFO @ 18686182861 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 18691869724 ps: (sram_ctrl_stress_all_vseq.sv:47) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] iteration[2]: starting sram_ctrl_bijection_vseq
  UVM_INFO @ 18709293949 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Update READBACK Value

1.sram_ctrl_stress_all.52707331245265553011974832021357600537367339062684680307998009412554373209320
Line 802, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 15408000237 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 15408198039 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Update READBACK Value
  UVM_INFO @ 15408296940 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value
  UVM_INFO @ 15419516709 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 15470395779 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value

... and 45 more failures.

Test sram_ctrl_stress_all_with_rand_reset has 22 failures.

1.sram_ctrl_stress_all_with_rand_reset.102907981001534452074236224683664231617972191426919773775101652161400438622233
Line 347, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 6874616208 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 6874882876 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 6875016210 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 6880453260 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq]
  Reset is issued for run 5/10

3.sram_ctrl_stress_all_with_rand_reset.107342377509990138456869279573964899241636394870314184294166432536026135683310
Line 320, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 2947476898 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 2947614830 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 2947683796 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Update READBACK Value
  UVM_INFO @ 2950491750 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq]
  Reset is issued for run 1/10

... and 20 more failures.

Test sram_ctrl_tl_intg_err has 3 failures.

2.sram_ctrl_tl_intg_err.108035035924017274409844209512674082267953925813870361019628524419490746383374
Line 521, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @ 435535979 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 435535979 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 435535979 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 439779875 ps: (dv_base_reg.sv:325) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds 2932097354 val
  UVM_INFO @ 440529881 ps: (dv_base_reg.sv:325) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds 3430389627 val

16.sram_ctrl_tl_intg_err.95808408018888456601162772983982753554074324785211745292112442281369064379765
Line 557, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @ 533969574 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 533969574 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 533969574 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 536939135 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Running run_tl_intg_err_vseq 17/20
  UVM_INFO @ 538139135 ps: (cip_tl_seq_item.sv:121) uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq.tl_seq.req] TL data or integrity bits have been flipped, see the changes as below:

... and 1 more failures.

UVM_ERROR (sram_ctrl_scoreboard.sv:422) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 45 failures:
- Test sram_ctrl_access_during_key_req has 45 failures.
  - 0.sram_ctrl_access_during_key_req.98281060321416442941294265941077889639348808725015224629164712368909535319509
    Line 310, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 1984830160 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 1984830160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.sram_ctrl_access_during_key_req.105070812234333596286427562860888130661683535937409874237994751357782175947151
    Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 3015746844 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 3015746844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 43 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:441) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 2 failures:
- Test sram_ctrl_access_during_key_req has 2 failures.
  - 2.sram_ctrl_access_during_key_req.113730634951306039356819430813599973323509197576540573139402293198288518182418
    Line 308, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 2111585202 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 2111585202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.sram_ctrl_access_during_key_req.97251540015939206707979445600413071940315150019146926451708175418342874953900
    Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 741179540 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 741179540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test sram_ctrl_tl_intg_err has 2 failures.

15.sram_ctrl_tl_intg_err.77358189521252908748575682954700462997068731242671926569034056951877866864582
Line 425, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_intg_err/latest/run.log

  UVM_ERROR @ 334448065 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 334448065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.sram_ctrl_tl_intg_err.75944541665394942446369184429319700052936534612964581375580606167483436091311
Line 476, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_intg_err/latest/run.log

  UVM_ERROR @ 725066211 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 725066211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 10.sram_ctrl_regwen.72629546978855436759839869603244255739967407983085469742068985663963574540078
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 15790968777 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xa25eb24b
  UVM_INFO @ 15790968777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 12.sram_ctrl_bijection.8970404392437234030218063560077901089392431394061945051031862388225057221532
    Line 1261, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 44.sram_ctrl_executable.31160069324583509351334037234917358524396562066469414152256317891693686769126
    Line 330, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 79551991930 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xe13b02f2
  UVM_INFO @ 79551991930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```