SRAM_CTRL/MAIN Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.804m	3.872ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	18.160us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	17.897us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.200s	250.175us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	61.860us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.620s	2.951ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	17.897us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	61.860us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.449m	277.195ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.985m	50.490ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	28.448m	44.875ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	10.311m	200.309ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	53.058m	662.105ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.564m	7.772ms	1	50	2.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.929m	20.521ms	50	50	100.00
V2	executable	sram_ctrl_executable	30.224m	82.552ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.974m	3.136ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.331m	30.120ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.799m	9.538ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.604m	4.948ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	28.244m	12.954ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.260s	2.601ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.739h	4.738s	1	50	2.00
V2	alert_test	sram_ctrl_alert_test	0.740s	10.572us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.600s	2.136ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.600s	2.136ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	18.160us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	17.897us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	61.860us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	99.846us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	18.160us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	17.897us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	61.860us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	99.846us	20	20	100.00
V2		TOTAL			639	740	86.35
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.224m	140.769ms	19	20	95.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.530s	1.160ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.910s	1.332ms	11	20	55.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.530s	1.160ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.910s	1.332ms	11	20	55.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	28.244m	12.954ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	17.897us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.224m	82.552ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.224m	82.552ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.224m	82.552ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.929m	20.521ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.224m	140.769ms	19	20	95.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.804m	3.872ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.804m	3.872ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.804m	3.872ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.224m	82.552ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.530s	1.160ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.929m	20.521ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.530s	1.160ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.530s	1.160ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.804m	3.872ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.530s	1.160ms	5	5	100.00
V2S		TOTAL			35	45	77.78
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.960m	15.172ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			908	1040	87.31

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	11	68.75
V2S	3	3	1	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.28	99.21	95.41	100.00	100.00	96.19	99.56	97.62

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 78 failures:

Test sram_ctrl_stress_all has 49 failures.

0.sram_ctrl_stress_all.3179228095599882794324366659016454937258523829548411155897741565958368945850
Line 304, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 3266200262 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 3266616922 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value
  UVM_INFO @ 3266741920 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Update READBACK Value
  UVM_INFO @ 3269783538 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 3274491796 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Update READBACK Value

1.sram_ctrl_stress_all.105515678505521827118481594044774084241921802936985830588473212925925940807219
Line 1798, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 89247381882 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 89247453310 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Update READBACK Value
  UVM_WARNING @ 89247453310 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 89247524738 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 89247596166 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_lc_escalation_vseq] Update READBACK Value

... and 47 more failures.

Test sram_ctrl_tl_intg_err has 8 failures.

0.sram_ctrl_tl_intg_err.20031529297072155688973683215265068531445033277917414289091003395487116561046
Line 601, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @ 152929046 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 152929046 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 152929046 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 154332943 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 154707955 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Running run_tl_intg_err_vseq 17/20

3.sram_ctrl_tl_intg_err.66411296796499614977519809454561633213899652113743704048172034952781685241720
Line 632, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @ 853738705 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 853738705 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 853738705 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 853738705 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 853770126 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value

... and 6 more failures.

Test sram_ctrl_stress_all_with_rand_reset has 21 failures.

1.sram_ctrl_stress_all_with_rand_reset.71147567092636528393038130797370011974825777826910494224804910726308152190387
Line 315, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 3611557902 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 3612224574 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 3612724578 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 3648391530 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value
  UVM_INFO @ 3753114590 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value

2.sram_ctrl_stress_all_with_rand_reset.69485888656792019447429312727444369461101170594708858958908326560024119287993
Line 311, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 1052665270 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 1052689660 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 1052860390 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 1053858431 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq]
  Reset is issued for run 4/10

... and 19 more failures.

UVM_ERROR (sram_ctrl_scoreboard.sv:422) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 48 failures:
- Test sram_ctrl_access_during_key_req has 48 failures.
  - 0.sram_ctrl_access_during_key_req.71232832254175969083638503922328763689501889626036149460082356002205786741156
    Line 302, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 6854898718 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 6854898718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.sram_ctrl_access_during_key_req.81192664214050049817685709106374110873687644902645663080546494573859279281425
    Line 299, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 6006995055 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 6006995055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 46 more failures.
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:
- Test sram_ctrl_tl_intg_err has 1 failures.
  - 14.sram_ctrl_tl_intg_err.87454175463433986340272059371919168648759352717147305608932247255657380847456
    Line 696, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 911887226 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 911887226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 15.sram_ctrl_passthru_mem_tl_intg_err.1374847414032291606233142892798348910110068482073266029671855671658794875057
    Line 897, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 4649151759 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 4649151759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 3.sram_ctrl_regwen.68526129585788659681756919227906945923770427566009966684419513558442676191888
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 18265819733 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x861948e4
  UVM_INFO @ 18265819733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (sram_ctrl_scoreboard.sv:441) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 1 failures:
- Test sram_ctrl_access_during_key_req has 1 failures.
  - 14.sram_ctrl_access_during_key_req.94371703953990462903878322732877712888806777106388359348097320531118384727647
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 846306962 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 846306962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 23.sram_ctrl_bijection.67488554623392359457479944704027235718647058375647308434508746007616575367282
    Line 1659, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 41.sram_ctrl_multiple_keys.73733750897675529045166603048014551918133519527303803238341476993815346016377
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 15604287008 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xb6dede5c
  UVM_INFO @ 15604287008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```