SRAM_CTRL/MAIN Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.543m	599.525us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	147.073us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	62.330us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.530s	663.259us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	24.914us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.690s	1.880ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	62.330us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	24.914us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.549m	197.559ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.238m	111.156ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	34.775m	153.850ms	48	50	96.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	9.776m	23.360ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	52.120m	179.843ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.824m	3.189ms	1	50	2.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.093m	62.508ms	50	50	100.00
V2	executable	sram_ctrl_executable	43.485m	119.771ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.739m	1.353ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.808m	348.276ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.669m	3.163ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.532m	6.487ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	33.242m	62.530ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.580s	4.195ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.945h	2.375s	0	50	0.00
V2	alert_test	sram_ctrl_alert_test	0.740s	84.241us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.000s	612.476us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.000s	612.476us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	147.073us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	62.330us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	24.914us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	22.267us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	147.073us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	62.330us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	24.914us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	22.267us	20	20	100.00
V2		TOTAL			637	740	86.08
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.220m	58.776ms	18	20	90.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.310s	912.184us	5	5	100.00
		sram_ctrl_tl_intg_err	2.720s	3.298ms	13	20	65.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.310s	912.184us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.720s	3.298ms	13	20	65.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.242m	62.530ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	62.330us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	43.485m	119.771ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	43.485m	119.771ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	43.485m	119.771ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.093m	62.508ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.220m	58.776ms	18	20	90.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.543m	599.525us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.543m	599.525us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.543m	599.525us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	43.485m	119.771ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.310s	912.184us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.093m	62.508ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.310s	912.184us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.310s	912.184us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.543m	599.525us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.310s	912.184us	5	5	100.00
V2S		TOTAL			36	45	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.672m	7.292ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			899	1040	86.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	1	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.23	99.21	95.41	100.00	100.00	96.19	99.56	97.26

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 80 failures:

Test sram_ctrl_stress_all has 48 failures.

0.sram_ctrl_stress_all.95406650109520020538065943561764986450042451907920781657771145504888113370195
Line 584, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 35309663403 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 35309898699 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value
  UVM_INFO @ 35310016347 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value
  UVM_INFO @ 35310428115 ps: (dv_base_reg.sv:325) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds          1 val
  UVM_INFO @ 35310722235 ps: (sram_ctrl_smoke_vseq.sv:101) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Performing 10000 random memory accesses!

1.sram_ctrl_stress_all.42107812666957334421314296044588939976896199024441981945872526070985313735701
Line 644, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 9812238010 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 9812413263 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Update READBACK Value
  UVM_INFO @ 9812475117 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Update READBACK Value
  UVM_INFO @ 9850546254 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 9854659545 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Update READBACK Value

... and 46 more failures.

Test sram_ctrl_tl_intg_err has 4 failures.

0.sram_ctrl_tl_intg_err.64837848023116181848315066740593944173090890274332220123329651793869743970141
Line 511, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @ 2107197996 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 2107197996 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 2107197996 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 2131957305 ps: (dv_base_reg.sv:325) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds 2841523317 val
  UVM_INFO @ 2134957305 ps: (dv_base_reg.sv:325) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds 3278573882 val

6.sram_ctrl_tl_intg_err.35957438246502407193118640618129971012419077169693438097320345770690623511802
Line 414, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @ 241659101 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 242028664 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 242224315 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 244550388 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 250485135 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value

... and 2 more failures.

Test sram_ctrl_stress_all_with_rand_reset has 26 failures.

1.sram_ctrl_stress_all_with_rand_reset.114348955225480536710697268018123771896669345879056915449217563396477375917871
Line 322, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 2342943659 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 2343143659 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Update READBACK Value
  UVM_INFO @ 2343343659 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 2357863659 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 2386103659 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value

2.sram_ctrl_stress_all_with_rand_reset.72792490650239069721786050111967077825332206283685821291276205888748908074884
Line 321, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 730504425 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 730607515 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 730720914 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 732153865 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Update READBACK Value
  UVM_INFO @ 762235527 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value

... and 24 more failures.

Test sram_ctrl_passthru_mem_tl_intg_err has 2 failures.

10.sram_ctrl_passthru_mem_tl_intg_err.43986588982495151127166983384276511088861633390223147945651811279765010265288
Line 793, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 8041966016 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 8042106016 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 8042266016 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 8059186016 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 8059886016 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value

11.sram_ctrl_passthru_mem_tl_intg_err.34679811994415339926964080329960899198511479409397934154876286271722072886722
Line 1544, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 53131655070 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 53132738399 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 53133155064 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 53160488288 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 53165821600 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value

UVM_ERROR (sram_ctrl_scoreboard.sv:422) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 45 failures:
- Test sram_ctrl_access_during_key_req has 45 failures.
  - 1.sram_ctrl_access_during_key_req.47913758816326201646398881827851520066661893649646373396556695945335865683701
    Line 291, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 1307774825 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 1307774825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.sram_ctrl_access_during_key_req.55650547652844216844157809120177232752594783414438287087755429033277973883277
    Line 294, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 2469304610 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 2469304610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 43 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:441) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 4 failures:
- Test sram_ctrl_access_during_key_req has 4 failures.
  - 0.sram_ctrl_access_during_key_req.112348059260207186298560779941094233452694678551111629650508450610564659700951
    Line 317, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 4521372331 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 4521372331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.sram_ctrl_access_during_key_req.74176938431965959823012269463088250563313994144537488314041007234866391467380
    Line 338, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 5639879000 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 5639879000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 3 failures:

Test sram_ctrl_tl_intg_err has 3 failures.

1.sram_ctrl_tl_intg_err.79484599511705793473106993817469289079702758095818574679931129984053932445410
Line 421, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_intg_err/latest/run.log

  UVM_ERROR @ 157760343 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 157760343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.sram_ctrl_tl_intg_err.22187189289179263238157587159397187892707181496192550457967148703535331022368
Line 532, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_intg_err/latest/run.log

  UVM_ERROR @ 1214091031 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 1214091031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 3 failures.
  - 3.sram_ctrl_stress_all_with_rand_reset.34124777156586704025255164212364560335398086665656650314045040611377925385764
    Line 305, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1053443001 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1053443001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.sram_ctrl_stress_all_with_rand_reset.100548562245285623639583773993580696085712164563543524889185314204239036700096
    Line 331, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4365932186 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4365932186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_multiple_keys has 2 failures.
  - 22.sram_ctrl_multiple_keys.112705151828030562528204242080274715851320285981914850933955752196798779160537
    Line 293, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 37420145853 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xc8bc417c
  UVM_INFO @ 37420145853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.sram_ctrl_multiple_keys.84680944986225656414961707046009611595980209082609727671517648168887674169365
    Line 318, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 59709515654 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x4f8b6b1c
  UVM_INFO @ 59709515654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 29.sram_ctrl_bijection.80364791610057818313547921646476969186207714648539718893617319899990819599168
    Line 1283, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.sram_ctrl_bijection.105673637855509945512519800979737914970352959972191084861304876126491829563673
    Line 1463, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 5.sram_ctrl_stress_all.113754486250096566635128470034558555757278789684045292266568132461463838372611
    Line 447, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 82834962518 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xc4a0ea3
  UVM_INFO @ 82834962518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 23.sram_ctrl_stress_all.38551081740728468499382999791253708821222353001378441633235054331377143320917
    Line 1754, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 701628289791 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x81283e2b
  UVM_INFO @ 701628289791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```