SRAM_CTRL/MAIN Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: `01a208901a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.001m	5.186ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	24.728us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	26.175us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.460s	263.356us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	21.134us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.230s	381.274us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	26.175us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	21.134us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.881m	57.653ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.995m	97.616ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	41.401m	55.018ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.844m	47.176ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	50.150m	172.725ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.055m	12.414ms	1	50	2.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.134m	23.386ms	50	50	100.00
V2	executable	sram_ctrl_executable	35.532m	32.990ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	3.022m	2.764ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.246m	55.412ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.910m	3.061ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.747m	4.889ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	32.983m	14.102ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.600s	4.219ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.795h	3.779s	1	50	2.00
V2	alert_test	sram_ctrl_alert_test	0.760s	32.353us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.330s	823.357us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.330s	823.357us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	24.728us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	26.175us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	21.134us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	155.048us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	24.728us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	26.175us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	21.134us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	155.048us	20	20	100.00
V2		TOTAL			642	740	86.76
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.122m	43.926ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.560s	943.244us	5	5	100.00
		sram_ctrl_tl_intg_err	4.410s	1.993ms	15	20	75.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.560s	943.244us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.410s	1.993ms	15	20	75.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	32.983m	14.102ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	26.175us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	35.532m	32.990ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	35.532m	32.990ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	35.532m	32.990ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.134m	23.386ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.122m	43.926ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.001m	5.186ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.001m	5.186ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.001m	5.186ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	35.532m	32.990ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.560s	943.244us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.134m	23.386ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.560s	943.244us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.560s	943.244us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.001m	5.186ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.560s	943.244us	5	5	100.00
V2S		TOTAL			40	45	88.89
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.725m	5.322ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			917	1040	88.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.23	99.21	95.41	100.00	100.00	96.19	99.56	97.26

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

has 72 failures:

Test sram_ctrl_stress_all_with_rand_reset has 20 failures.

0.sram_ctrl_stress_all_with_rand_reset.57418179465345481914005562896382992169623317779033520849779468956659892801370
Line 301, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 2415430565 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 2415530565 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Update READBACK Value
  UVM_INFO @ 2415630565 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 2542130565 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Running run_tl_errors_vseq 7/830
  UVM_INFO @ 2605930565 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Update READBACK Value

2.sram_ctrl_stress_all_with_rand_reset.27256131426055651867812337925605510541673696932136815378400202419033884740993
Line 379, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 4501095098 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 4501455098 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 4501775098 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Update READBACK Value
  UVM_INFO @ 4642895098 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 4735535098 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value

... and 18 more failures.

Test sram_ctrl_stress_all has 49 failures.

0.sram_ctrl_stress_all.37272221279277721281925864103439202281945666296455753009769023376447769272027
Line 1700, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 73089947582 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 73090212886 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Update READBACK Value
  UVM_INFO @ 73090335334 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 73150212406 ps: (sram_ctrl_smoke_vseq.sv:62) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] iteration: 3
  UVM_INFO @ 73150212406 ps: (sram_ctrl_smoke_vseq.sv:101) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Performing 7643 random memory accesses!

1.sram_ctrl_stress_all.56354105990061951832586263875612615555096472383965474339648718941897247846298
Line 919, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 84612388781 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 84613127907 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 84613519209 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value
  UVM_INFO @ 84614519203 ps: (dv_base_reg.sv:325) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds          1 val
  UVM_INFO @ 84614780071 ps: (sram_ctrl_smoke_vseq.sv:101) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Performing 7785 random memory accesses!

... and 47 more failures.

Test sram_ctrl_tl_intg_err has 3 failures.

1.sram_ctrl_tl_intg_err.57363935220073661959351425180076913034622489247529673821453587951712127583851
Line 486, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @  95115630 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @  95115630 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @  95115630 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @  96503041 ps: (dv_base_reg.sv:325) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds 3202306676 val
  UVM_INFO @  96653041 ps: (dv_base_reg.sv:325) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds 1442662179 val

10.sram_ctrl_tl_intg_err.75276194935882589297714147741921697297733933262213568816696215810637607282527
Line 459, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @  99703546 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @  99866810 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @  99958646 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 100070890 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 100672926 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value

... and 1 more failures.

UVM_ERROR (sram_ctrl_scoreboard.sv:422) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 46 failures:
- Test sram_ctrl_access_during_key_req has 46 failures.
  - 0.sram_ctrl_access_during_key_req.21722448729744331598640260736581014511925356750467183438647933604033204189065
    Line 327, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 2643137251 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 2643137251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.sram_ctrl_access_during_key_req.112125015162074073847582381077241529394808894304327067027615682508336390277121
    Line 283, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 720460260 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 720460260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 44 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:441) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 3 failures:
- Test sram_ctrl_access_during_key_req has 3 failures.
  - 3.sram_ctrl_access_during_key_req.42155976419742344689460917318833987559927994904755920582660052282373712411130
    Line 302, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 3157436124 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 3157436124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.sram_ctrl_access_during_key_req.95071003098840608409977897784263750536517251471121525107571588929489341018674
    Line 338, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 12414187287 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 12414187287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test sram_ctrl_tl_intg_err has 2 failures.

9.sram_ctrl_tl_intg_err.113592260364580575565299865015931957154141736832895498489134412917007293282436
Line 578, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_intg_err/latest/run.log

  UVM_ERROR @ 172635706 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 172635706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.sram_ctrl_tl_intg_err.68916437691335551339410170031255210069005118817838194162268286488051500475619
Line 374, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_intg_err/latest/run.log

  UVM_ERROR @ 168359127 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 168359127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---