SRAM_CTRL/MAIN Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: `a182fcef27`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.971m	15.711ms	48	50	96.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.780s	180.035us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	12.951us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.730s	2.797ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.790s	73.962us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.000s	3.519ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	12.951us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	73.962us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.981m	21.563ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.021m	6.701ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	39.600m	15.945ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.302m	34.568ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	48.560m	117.805ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.980m	3.971ms	0	50	0.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.782m	228.628ms	50	50	100.00
V2	executable	sram_ctrl_executable	30.738m	31.516ms	48	50	96.00
V2	partial_access	sram_ctrl_partial_access	2.690m	2.034ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.907m	23.602ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	3.037m	1.528ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.982m	2.541ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	33.652m	52.929ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.130s	6.704ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.903h	791.690ms	0	50	0.00
V2	alert_test	sram_ctrl_alert_test	0.720s	14.735us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.900s	172.777us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.900s	172.777us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.780s	180.035us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	12.951us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	73.962us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	300.068us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.780s	180.035us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	12.951us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	73.962us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	300.068us	20	20	100.00
V2		TOTAL			637	740	86.08
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.300m	88.137ms	19	20	95.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.530s	485.980us	5	5	100.00
		sram_ctrl_tl_intg_err	2.730s	272.670us	16	20	80.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.530s	485.980us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.730s	272.670us	16	20	80.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.652m	52.929ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	12.951us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.738m	31.516ms	48	50	96.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.738m	31.516ms	48	50	96.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.738m	31.516ms	48	50	96.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.782m	228.628ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.300m	88.137ms	19	20	95.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.971m	15.711ms	48	50	96.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.971m	15.711ms	48	50	96.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.971m	15.711ms	48	50	96.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.738m	31.516ms	48	50	96.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.530s	485.980us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.782m	228.628ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.530s	485.980us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.530s	485.980us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.971m	15.711ms	48	50	96.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.530s	485.980us	5	5	100.00
V2S		TOTAL			40	45	88.89
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.333m	6.257ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			899	1040	86.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	12	75.00
V2S	3	3	1	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.28	99.21	95.41	100.00	100.00	96.19	99.56	97.62

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 83 failures:

Test sram_ctrl_stress_all_with_rand_reset has 30 failures.

0.sram_ctrl_stress_all_with_rand_reset.47497104812179666314405784232679613542233310601933167270979436324593740415971
Line 325, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 3316237668 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 3316437668 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 3316517668 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 3319767591 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq]
  Reset is issued for run 3/10

3.sram_ctrl_stress_all_with_rand_reset.2998140853179223150901906101515956292061966690639354981401144609745831938615
Line 288, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 1644492043 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 1644872043 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 1645032043 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 1659450186 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq]
  Reset is issued for run 1/5

... and 28 more failures.

Test sram_ctrl_stress_all has 48 failures.

0.sram_ctrl_stress_all.77530360271615808791465813425527803207282367656323016062319757209745201674481
Line 757, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 11743755245 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 11743786172 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Update READBACK Value
  UVM_INFO @ 11743982043 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 11744002661 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_lc_escalation_vseq] Update READBACK Value
  UVM_INFO @ 11788960210 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_lc_escalation_vseq] Update READBACK Value

1.sram_ctrl_stress_all.44182118596534136272071844606590535231044708527429804982311129843978565722603
Line 571, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 7832003140 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 7832125588 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 7832176608 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_lc_escalation_vseq] Update READBACK Value
  UVM_INFO @ 7834156184 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Update READBACK Value
  UVM_INFO @ 7881829272 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_lc_escalation_vseq] Update READBACK Value

... and 46 more failures.

Test sram_ctrl_tl_intg_err has 4 failures.

1.sram_ctrl_tl_intg_err.65334409738444894813986084261104861323667216060708659369381168123498191293843
Line 449, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @ 148651509 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 148651509 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 148651509 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 160806589 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 161010669 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value

8.sram_ctrl_tl_intg_err.4232471343665767953511569760302409450799616105063956824714943774166069879994
Line 425, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @ 122966651 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 122966651 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 122966651 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 124960702 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 125238477 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value

... and 2 more failures.

Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.

15.sram_ctrl_passthru_mem_tl_intg_err.100341522322168822132231347884245198942101705013050917436915890892505979751105
Line 629, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 41909168611 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 41909418611 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 41909793611 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 41964043611 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 42138418611 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value

UVM_ERROR (sram_ctrl_scoreboard.sv:422) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 44 failures:
- Test sram_ctrl_access_during_key_req has 44 failures.
  - 0.sram_ctrl_access_during_key_req.18495787567754073649083894820695454680471650845954537915475608062045450677763
    Line 305, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 3818288963 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 3818288963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.sram_ctrl_access_during_key_req.38947825975318717753568914902358814086064723644496822201739364654242486289568
    Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 2034622673 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 2034622673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 42 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:441) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 6 failures:
- Test sram_ctrl_access_during_key_req has 6 failures.
  - 17.sram_ctrl_access_during_key_req.55472034432645084322813831953801532039513284363607468978198307787422769263103
    Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 4225241041 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 4225241041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.sram_ctrl_access_during_key_req.77880889546385294099713914049749303531425045397785249085991757752808233718317
    Line 326, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 10170706042 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 10170706042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_smoke has 2 failures.
  - 4.sram_ctrl_smoke.74642104806167589842334927931045952635245627896706788435349023480624185410727
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 18244072867 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x3cfd5107
  UVM_INFO @ 18244072867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.sram_ctrl_smoke.71071889136371403652341554693882144233270592186798031262435029356245556488522
    Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 21010890203 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x60f5bc27
  UVM_INFO @ 21010890203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 7.sram_ctrl_multiple_keys.58066955154291191653189837888213418397648191081382394298691995861535635210751
    Line 355, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 85321649721 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x15462882
  UVM_INFO @ 85321649721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 1 failures.
  - 10.sram_ctrl_stress_all.38094142991548630573585313930264536721246074205711265721083525206197764941010
    Line 623, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 193642314030 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x50dc15e4
  UVM_INFO @ 193642314030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_executable has 2 failures.
  - 8.sram_ctrl_executable.106956328093339126477960463168298884041587840931854424400284334782455853501788
    Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 29155498487 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x5c52dcd8
  UVM_INFO @ 29155498487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.sram_ctrl_executable.87208774760355379478477100506933701113931322581522276088417646249864652023085
    Line 361, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 81582800189 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x786028f0
  UVM_INFO @ 81582800189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 15.sram_ctrl_stress_all_with_rand_reset.90820167392020111688020526817646241076338400471222892363306875660984767392840
    Line 296, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4120473559 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4120473559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 28.sram_ctrl_stress_all.52893929351801477305241511418381251425939216706408555836801784824042722274050
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:35a19cc2-571f-44bc-9342-071c25eeae19
```