SRAM_CTRL/MAIN Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.477m	5.150ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	19.728us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	11.057us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.650s	1.191ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	18.676us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.080s	6.995ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	11.057us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	18.676us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.300m	89.794ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.084m	79.389ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	35.737m	185.439ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.796m	8.123ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	49.896m	351.788ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	30.987m	420.607ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.231m	208.404ms	50	50	100.00
V2	executable	sram_ctrl_executable	35.218m	116.371ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.818m	3.354ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.525m	25.368ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.348m	818.366us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.733m	3.390ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.711m	19.742ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.260s	6.684ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.577h	895.288ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.790s	15.056us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.220s	497.635us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.220s	497.635us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	19.728us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	11.057us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	18.676us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	88.962us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	19.728us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	11.057us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	18.676us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	88.962us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.141m	47.008ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.080s	1.951ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.820s	1.155ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.080s	1.951ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.820s	1.155ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.711m	19.742ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	11.057us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	35.218m	116.371ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	35.218m	116.371ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	35.218m	116.371ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.231m	208.404ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.141m	47.008ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.477m	5.150ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.477m	5.150ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.477m	5.150ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	35.218m	116.371ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.080s	1.951ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.231m	208.404ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.080s	1.951ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.080s	1.951ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.477m	5.150ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.080s	1.951ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.963m	4.691ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1033	1040	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.22	99.21	95.17	100.00	100.00	96.19	99.56	97.44

Failure Buckets

Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test sram_ctrl_stress_all has 2 failures.
  - 3.sram_ctrl_stress_all.13864988561022819579283876309929806679067817677359976145293441095389056252355
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:4c0ee7ae-25ea-4989-bc8a-1dbf09740ff5
```
  - 46.sram_ctrl_stress_all.71603170597616602736897578222458893113402716516403948301367256786346128003806
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:caf69783-cb85-430d-800b-634e7a33ef0c
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 13.sram_ctrl_bijection.3708569120679388396426121822524208803567286527016175574534254918429011006244
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.sram_ctrl_bijection.14709498362285507285418390471959103786244690788178556719909783729419092369021
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 2 failures.
  - 30.sram_ctrl_stress_all_with_rand_reset.106726132241983608733502428890183370620672361858490415903259897414916501316093
    Line 306, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7871571097 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7871571097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.sram_ctrl_stress_all_with_rand_reset.25677543415981506339247604699072132052638370615865995148340396168975513878801
    Line 317, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5246763528 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5246763528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 40.sram_ctrl_multiple_keys.32244382619815460631868136405619925784306863411987054279403872567554348253363
    Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 100234990373 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x68f52b29
  UVM_INFO @ 100234990373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `b29ffbb03c`