SRAM_CTRL/MAIN Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.944m	1.337ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.780s	21.569us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	48.335us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.350s	180.958us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	21.638us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.590s	696.877us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	48.335us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	21.638us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.816m	82.653ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.073m	19.961ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	41.303m	198.543ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.793m	14.295ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	43.500m	460.168ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	42.849m	58.915ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.940m	62.101ms	50	50	100.00
V2	executable	sram_ctrl_executable	27.608m	36.097ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.681m	896.489us	50	50	100.00
		sram_ctrl_partial_access_b2b	11.059m	101.872ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.790m	3.048ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.987m	3.126ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	34.839m	25.216ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.070s	3.728ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.735h	395.574ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.740s	187.258us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.050s	217.483us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.050s	217.483us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.780s	21.569us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	48.335us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	21.638us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	160.653us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.780s	21.569us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	48.335us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	21.638us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	160.653us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.101m	78.437ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.850s	14.885us	0	5	0.00
		sram_ctrl_tl_intg_err	2.970s	1.026ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.850s	14.885us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.970s	1.026ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	34.839m	25.216ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	48.335us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	27.608m	36.097ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	27.608m	36.097ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	27.608m	36.097ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.940m	62.101ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.101m	78.437ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.944m	1.337ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.944m	1.337ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.944m	1.337ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	27.608m	36.097ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.850s	14.885us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.940m	62.101ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.850s	14.885us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.850s	14.885us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.944m	1.337ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.850s	14.885us	0	5	0.00
V2S		TOTAL			40	45	88.89
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.927m	2.722ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	16	100.00
V2S	3	3	2	66.67
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.38	99.03	92.48	99.31	100.00	95.35	98.40	97.07

Failure Buckets

• Offending '(!$isunknown(tl_o.d_valid))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 0.sram_ctrl_sec_cm.66805035682960426859025324186494568150968065442501833701729228329763740956485
      Line 283, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(tl_o.d_valid))'
        UVM_ERROR @  38298253 ps: (tlul_adapter_sram.sv:623) [ASSERT FAILED] TlOutValidKnown_A
        UVM_INFO @  38298253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 4.sram_ctrl_sec_cm.31885042990063380028251552988040953424751891599421828541814728808993590384404
      Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(tl_o.d_valid))'
        UVM_ERROR @   4274073 ps: (tlul_adapter_sram.sv:623) [ASSERT FAILED] TlOutValidKnown_A
        UVM_INFO @   4274073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 1.sram_ctrl_sec_cm.5624510764256710457833693111914601822761376971043572275490876478275702150950
      Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  14236670 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  14236670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 2.sram_ctrl_sec_cm.47697337242685130967827379873200383486675155856175139824811147868151603869168
      Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   8299223 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   8299223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 3.sram_ctrl_sec_cm.81482715179523334543620286356247122859572530877240197515009540825196097643151
      Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  14885074 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  14885074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.06.06_11.13.37
• 2024.06.05_04.08.37
• 2024.06.03_07.08.44
• 2024.05.31_05.00.10
• 2024.05.29_03.31.29
• 2024.05.27_04.37.03
• 2024.05.24_04.41.48