SRAM_CTRL/MAIN Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: `302b24f3c6`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.587m	4.019ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	22.463us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	25.344us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.180s	245.298us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.790s	21.668us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.890s	7.126ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	25.344us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	21.668us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.273m	125.622ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.066m	23.177ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	31.522m	153.949ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.089m	24.376ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	50.663m	958.810ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	35.005m	155.725ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.345m	219.384ms	50	50	100.00
V2	executable	sram_ctrl_executable	40.449m	10.096ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.618m	887.464us	50	50	100.00
		sram_ctrl_partial_access_b2b	11.375m	28.230ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	3.292m	784.610us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.406m	798.958us	50	50	100.00
V2	regwen	sram_ctrl_regwen	42.314m	19.494ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.800s	4.190ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.349h	171.286ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.750s	18.930us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.730s	630.736us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.730s	630.736us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	22.463us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	25.344us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	21.668us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.880s	31.433us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	22.463us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	25.344us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	21.668us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.880s	31.433us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.183m	140.705ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.820s	23.312us	0	5	0.00
		sram_ctrl_tl_intg_err	4.350s	1.653ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.820s	23.312us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.350s	1.653ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	42.314m	19.494ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	25.344us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	40.449m	10.096ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	40.449m	10.096ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	40.449m	10.096ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.345m	219.384ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.183m	140.705ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.587m	4.019ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.587m	4.019ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.587m	4.019ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	40.449m	10.096ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.820s	23.312us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.345m	219.384ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.820s	23.312us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.820s	23.312us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.587m	4.019ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.820s	23.312us	0	5	0.00
V2S		TOTAL			40	45	88.89
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.379m	3.549ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1029	1040	98.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.38	99.03	92.48	99.31	100.00	95.35	98.40	97.07

Failure Buckets

Offending '(!$isunknown(rdata_o))' has 2 failures:
- Test sram_ctrl_sec_cm has 2 failures.
  - 0.sram_ctrl_sec_cm.24784559798531196864662307818172017817350874305253025419743239085490319939403
    Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   3139140 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3139140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.sram_ctrl_sec_cm.1486440297005347636837028984618491143459865889567862193763550490128272229508
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @  23311655 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  23311655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

1.sram_ctrl_stress_all.60670429919118127878673853987791403127459074742826150392881675299616702041555
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 1225575339 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 1225575339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.sram_ctrl_stress_all.65158415243556282081778147816118449829733621360837041235812986407562567519553
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 1034630600 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 1034630600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown(tl_o.d_valid))' has 2 failures:
- Test sram_ctrl_sec_cm has 2 failures.
  - 2.sram_ctrl_sec_cm.5688263732526409685509172823345545889548337733623517886860694656855314342520
    Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(tl_o.d_valid))'
  UVM_ERROR @   1395407 ps: (tlul_adapter_sram.sv:679) [ASSERT FAILED] TlOutValidKnown_A
  UVM_INFO @   1395407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 3.sram_ctrl_sec_cm.63148089615534933970184300898131031267753424396836135362189515459778850509513
    Line 275, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(tl_o.d_valid))'
  UVM_ERROR @  19609769 ps: (tlul_adapter_sram.sv:679) [ASSERT FAILED] TlOutValidKnown_A
  UVM_INFO @  19609769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 4.sram_ctrl_sec_cm.104029186520606277280941600064191015300062425797722774714381517541071571708009
    Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @  12241529 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  12241529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 15.sram_ctrl_multiple_keys.58623691687784047945226700924598942288138378621363337794811140592361075171831
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 24941346595 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xc19a78c5
  UVM_INFO @ 24941346595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 21.sram_ctrl_regwen.80373718402722379028806894887939931843568936336296624402097225850926325380671
    Line 314, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 139481335942 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x252c1dcd
  UVM_INFO @ 139481335942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 30.sram_ctrl_executable.93359939980156823458872737482836617764377004103799605880979225330355421433834
    Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 64687150460 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x63b395dc
  UVM_INFO @ 64687150460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 33.sram_ctrl_stress_all_with_rand_reset.30916374726278215834867814236028517914489068708027676188552942539908639884665
    Line 325, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2024262141 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2024262141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```