SRAM_CTRL/MAIN Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: f92a5ee77b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.522m 483.165us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.740s 16.720us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.730s 13.628us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.340s 119.487us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 69.267us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.340s 2.710ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.730s 13.628us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 69.267us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.459m 71.710ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.033m 26.655ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 30.509m 42.477ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.985m 7.002ms 50 50 100.00
V2 bijection sram_ctrl_bijection 47.417m 359.131ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 32.182m 18.868ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.119m 113.565ms 50 50 100.00
V2 executable sram_ctrl_executable 32.480m 15.464ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.883m 16.872ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.143m 200.284ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.503m 786.322us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.731m 1.572ms 50 50 100.00
V2 regwen sram_ctrl_regwen 32.414m 4.643ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.830s 4.206ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.956h 631.032ms 46 50 92.00
V2 alert_test sram_ctrl_alert_test 0.690s 58.930us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.920s 599.265us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.920s 599.265us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.740s 16.720us 5 5 100.00
sram_ctrl_csr_rw 0.730s 13.628us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 69.267us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.840s 44.747us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.740s 16.720us 5 5 100.00
sram_ctrl_csr_rw 0.730s 13.628us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 69.267us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.840s 44.747us 20 20 100.00
V2 TOTAL 736 740 99.46
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.023m 28.235ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 0.900s 27.849us 0 5 0.00
sram_ctrl_tl_intg_err 3.040s 489.556us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 0.900s 27.849us 0 5 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.040s 489.556us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 32.414m 4.643ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.730s 13.628us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 32.480m 15.464ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 32.480m 15.464ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 32.480m 15.464ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.119m 113.565ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.023m 28.235ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.522m 483.165us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.522m 483.165us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.522m 483.165us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 32.480m 15.464ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 0.900s 27.849us 0 5 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.119m 113.565ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 0.900s 27.849us 0 5 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 0.900s 27.849us 0 5 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.522m 483.165us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 0.900s 27.849us 0 5 0.00
V2S TOTAL 40 45 88.89
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.610m 3.926ms 45 50 90.00
V3 TOTAL 45 50 90.00
TOTAL 1026 1040 98.65

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 15 93.75
V2S 3 3 2 66.67
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.38 99.03 92.48 99.31 100.00 95.35 98.40 97.07

Failure Buckets

Past Results