SRAM_CTRL/MAIN Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.760m	2.552ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	17.153us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.790s	17.155us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.410s	349.782us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.830s	21.437us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.870s	4.286ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.790s	17.155us	20	20	100.00
		sram_ctrl_csr_aliasing	0.830s	21.437us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.018m	20.911ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.112m	11.563ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	28.082m	22.106ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.754m	6.541ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	48.301m	330.430ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	33.670m	64.347ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.994m	22.123ms	50	50	100.00
V2	executable	sram_ctrl_executable	30.507m	9.753ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.769m	1.381ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.410m	25.553ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.664m	767.300us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.537m	2.010ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	30.772m	78.107ms	48	50	96.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.590s	6.728ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.405h	4.573s	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.730s	21.699us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.710s	131.672us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.710s	131.672us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	17.153us	5	5	100.00
		sram_ctrl_csr_rw	0.790s	17.155us	20	20	100.00
		sram_ctrl_csr_aliasing	0.830s	21.437us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	25.143us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	17.153us	5	5	100.00
		sram_ctrl_csr_rw	0.790s	17.155us	20	20	100.00
		sram_ctrl_csr_aliasing	0.830s	21.437us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	25.143us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.172m	63.976ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.880s	32.730us	0	5	0.00
		sram_ctrl_tl_intg_err	2.650s	364.495us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.880s	32.730us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.650s	364.495us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	30.772m	78.107ms	48	50	96.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.790s	17.155us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.507m	9.753ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.507m	9.753ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.507m	9.753ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.994m	22.123ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.172m	63.976ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.760m	2.552ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.760m	2.552ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.760m	2.552ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.507m	9.753ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.880s	32.730us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.994m	22.123ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.880s	32.730us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.880s	32.730us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.760m	2.552ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.880s	32.730us	0	5	0.00
V2S		TOTAL			40	45	88.89
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.168m	7.688ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1027	1040	98.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.38	99.03	92.48	99.31	100.00	95.35	98.40	97.07

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
- Test sram_ctrl_sec_cm has 4 failures.
  - 0.sram_ctrl_sec_cm.73516374365385824314859610674704965458370508333531061549478642188594008056134
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @  12124816 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  12124816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.sram_ctrl_sec_cm.82891289476452144967177445056161244108620122625295681877430889795328383424894
    Line 290, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @  32729564 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  32729564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 10.sram_ctrl_stress_all.94308332742947612792327498572538327238432805355562750625984658662995893021723
    Line 515, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 2256314125351 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xe863007d
  UVM_INFO @ 2256314125351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_regwen has 2 failures.
  - 18.sram_ctrl_regwen.85392334863120757340141455193741258889325554222722015884663225356926237599198
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 30068584665 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x3a23c7e7
  UVM_INFO @ 30068584665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.sram_ctrl_regwen.8056307276039683247882119375717934067952027165845166090618985211710679962586
    Line 299, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 113219630324 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x4435c7c2
  UVM_INFO @ 113219630324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 1.sram_ctrl_bijection.44941975780741775380032357413851311111451124243963418045946602061581496600824
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.sram_ctrl_bijection.2444404993486373872012682586621281395129115802863756021147596071372053321874
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(tl_o.d_valid))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 1.sram_ctrl_sec_cm.23606712330675554969754517162634694187317256660724034329303062169148458607329
    Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(tl_o.d_valid))'
  UVM_ERROR @   6249289 ps: (tlul_adapter_sram.sv:679) [ASSERT FAILED] TlOutValidKnown_A
  UVM_INFO @   6249289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 8.sram_ctrl_stress_all_with_rand_reset.49469764836054757351649707195907747017510870239488955891532449590606548834830
    Line 307, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5439858657 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5439858657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 18.sram_ctrl_stress_all.87522349165705518361189684892932931240828885115047838514559315638701507303687
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 21125047988 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xfe0f0409
  UVM_INFO @ 21125047988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 33.sram_ctrl_multiple_keys.42164948123305883831303583665151877044413318791901268794597173497511724567993
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 27823993336 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xbe6117d3
  UVM_INFO @ 27823993336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a8c9c17a8c`