SRAM_CTRL/MAIN Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.997m 6.038ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.710s 37.826us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.730s 17.329us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.240s 174.983us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.810s 16.870us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 8.880s 10.009ms 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.730s 17.329us 20 20 100.00
sram_ctrl_csr_aliasing 0.810s 16.870us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.184m 138.066ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.015m 19.175ms 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 28.820m 18.473ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.216m 10.173ms 50 50 100.00
V2 bijection sram_ctrl_bijection 49.213m 352.007ms 48 50 96.00
V2 access_during_key_req sram_ctrl_access_during_key_req 37.344m 44.299ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.266m 102.681ms 50 50 100.00
V2 executable sram_ctrl_executable 37.568m 177.775ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.768m 1.948ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.450m 90.084ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.580m 1.593ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.667m 7.103ms 50 50 100.00
V2 regwen sram_ctrl_regwen 29.623m 43.652ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 3.940s 1.695ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.646h 1.486s 47 50 94.00
V2 alert_test sram_ctrl_alert_test 0.710s 22.081us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.350s 527.842us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.350s 527.842us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.710s 37.826us 5 5 100.00
sram_ctrl_csr_rw 0.730s 17.329us 20 20 100.00
sram_ctrl_csr_aliasing 0.810s 16.870us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 21.764us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.710s 37.826us 5 5 100.00
sram_ctrl_csr_rw 0.730s 17.329us 20 20 100.00
sram_ctrl_csr_aliasing 0.810s 16.870us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 21.764us 20 20 100.00
V2 TOTAL 734 740 99.19
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.626m 140.945ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 0.890s 15.695us 0 5 0.00
sram_ctrl_tl_intg_err 2.610s 263.630us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 0.890s 15.695us 0 5 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.610s 263.630us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 29.623m 43.652ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.730s 17.329us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 37.568m 177.775ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 37.568m 177.775ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 37.568m 177.775ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.266m 102.681ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.626m 140.945ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.997m 6.038ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.997m 6.038ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.997m 6.038ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 37.568m 177.775ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 0.890s 15.695us 0 5 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.266m 102.681ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 0.890s 15.695us 0 5 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 0.890s 15.695us 0 5 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.997m 6.038ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 0.890s 15.695us 0 5 0.00
V2S TOTAL 40 45 88.89
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.452m 6.256ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1028 1040 98.85

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 13 81.25
V2S 3 3 2 66.67
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.39 99.02 92.48 99.31 100.00 95.33 98.54 97.07

Failure Buckets

Past Results