SRAM_CTRL/MAIN Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.787m	450.420us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	16.038us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	29.482us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.260s	183.790us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.790s	25.895us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.180s	1.555ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	29.482us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	25.895us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.801m	230.575ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.164m	45.607ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	36.868m	35.821ms	48	50	96.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.421m	30.731ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	50.710m	311.418ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	35.085m	59.758ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.647m	123.901ms	50	50	100.00
V2	executable	sram_ctrl_executable	29.536m	42.057ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.131m	1.377ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.029m	97.878ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	3.452m	771.681us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.875m	785.208us	50	50	100.00
V2	regwen	sram_ctrl_regwen	28.607m	61.082ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.140s	6.715ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.661h	301.605ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.740s	13.367us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.660s	295.224us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.660s	295.224us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	16.038us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	29.482us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	25.895us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	50.261us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	16.038us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	29.482us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	25.895us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	50.261us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	59.070s	29.389ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.360s	272.038us	5	5	100.00
		sram_ctrl_tl_intg_err	3.120s	555.706us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.360s	272.038us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.120s	555.706us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	28.607m	61.082ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	29.482us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.536m	42.057ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.536m	42.057ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.536m	42.057ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.647m	123.901ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	59.070s	29.389ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.787m	450.420us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.787m	450.420us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.787m	450.420us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.536m	42.057ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.360s	272.038us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.647m	123.901ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.360s	272.038us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.360s	272.038us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.787m	450.420us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.360s	272.038us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.550m	7.449ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1036	1040	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:

  • Test sram_ctrl_multiple_keys has 2 failures.

    • 8.sram_ctrl_multiple_keys.37823059329624428681134808088674230687164344743044288525820797302037244334494
      Line 336, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 295485434310 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x2b44d2bf
        UVM_INFO @ 295485434310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.sram_ctrl_multiple_keys.47529160523919059549023924893457611901208254107410569120100129244378691732405
      Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 67729103760 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xdc8d1405
        UVM_INFO @ 67729103760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 9.sram_ctrl_stress_all.101564554525944973274657361229032792951655422011591863546258336957842161142324
      Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest/run.log

        Job ID: smart:0a913611-735f-4afa-bd1c-5471d2f7234c
      

• UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 42.sram_ctrl_stress_all_with_rand_reset.4845136291736353935676105395175939321782596396775392201610873498064303329472
      Line 308, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6155802297 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6155802297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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