SRAM_CTRL/MAIN Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.331m	3.215ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.770s	60.251us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	15.024us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.000s	167.513us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	33.175us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.330s	1.423ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	15.024us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	33.175us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.803m	86.175ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.893m	23.574ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	27.392m	29.322ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.348m	93.675ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	45.324m	293.054ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	37.059m	45.996ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.693m	62.954ms	50	50	100.00
V2	executable	sram_ctrl_executable	26.158m	27.340ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	1.814m	8.091ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.543m	102.774ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.134m	1.592ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.213m	6.517ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	26.581m	222.760ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.140s	3.360ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.593h	241.600ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.730s	13.718us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.730s	591.970us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.730s	591.970us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.770s	60.251us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	15.024us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	33.175us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	39.923us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.770s	60.251us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	15.024us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	33.175us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	39.923us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.009m	28.253ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.590s	3.116ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.490s	2.072ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.590s	3.116ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.490s	2.072ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	26.581m	222.760ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	15.024us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.158m	27.340ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.158m	27.340ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.158m	27.340ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.693m	62.954ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.009m	28.253ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.331m	3.215ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.331m	3.215ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.331m	3.215ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.158m	27.340ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.590s	3.116ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.693m	62.954ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.590s	3.116ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.590s	3.116ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.331m	3.215ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.590s	3.116ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.331m	2.530ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1034	1040	99.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_stress_all has 2 failures.
  - 0.sram_ctrl_stress_all.34643641869803182797802457735719604136933182760161703326547616425111497168309
    Line 318, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 149482722259 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xf8f0ef49
  UVM_INFO @ 149482722259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.sram_ctrl_stress_all.29470524011059649701873973583196055041711104997554927182506792781541281484363
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 23208258250 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xc0d484c3
  UVM_INFO @ 23208258250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 6.sram_ctrl_bijection.104249556685082896338529114826775499410902685771659188151091185942046304341213
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.sram_ctrl_bijection.93564977046276718602969089788241787527216083226772537659170552502124811580945
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 43.sram_ctrl_executable.34652167833711511515284783038526091083163194767558391412162511087740903582373
    Line 296, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 124538614590 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x1243c7ad
  UVM_INFO @ 124538614590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:749) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 45.sram_ctrl_stress_all_with_rand_reset.65889376641291255865874888345405722830169702254688249615617267469229388173233
    Line 375, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9195164038 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 9195164038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `3e678c112b`