SRAM_CTRL/MAIN Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.834m 1.787ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.700s 39.427us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.690s 31.841us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.240s 460.971us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.750s 118.924us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.630s 904.382us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.690s 31.841us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 118.924us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.703m 188.008ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.086m 5.239ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 31.311m 61.383ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.354m 6.760ms 50 50 100.00
V2 bijection sram_ctrl_bijection 50.601m 420.436ms 48 50 96.00
V2 access_during_key_req sram_ctrl_access_during_key_req 36.164m 65.097ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.949m 129.563ms 50 50 100.00
V2 executable sram_ctrl_executable 33.555m 57.568ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.825m 2.333ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.672m 44.927ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.656m 812.457us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.511m 1.533ms 50 50 100.00
V2 regwen sram_ctrl_regwen 34.600m 18.550ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.410s 6.707ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.367h 248.639ms 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.750s 41.401us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.410s 558.106us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.410s 558.106us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.700s 39.427us 5 5 100.00
sram_ctrl_csr_rw 0.690s 31.841us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 118.924us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.860s 94.014us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.700s 39.427us 5 5 100.00
sram_ctrl_csr_rw 0.690s 31.841us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 118.924us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.860s 94.014us 20 20 100.00
V2 TOTAL 737 740 99.59
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 55.860s 22.008ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.270s 1.059ms 5 5 100.00
sram_ctrl_tl_intg_err 2.580s 753.973us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.270s 1.059ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.580s 753.973us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 34.600m 18.550ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.690s 31.841us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 33.555m 57.568ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 33.555m 57.568ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 33.555m 57.568ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.949m 129.563ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 55.860s 22.008ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.834m 1.787ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.834m 1.787ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.834m 1.787ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 33.555m 57.568ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.270s 1.059ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.949m 129.563ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.270s 1.059ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.270s 1.059ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.834m 1.787ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.270s 1.059ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.523m 2.150ms 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 1034 1040 99.42

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.94 99.19 94.27 99.72 100.00 96.03 99.12 97.26

Failure Buckets

Past Results