SRAM_CTRL/MAIN Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.633m 1.016ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.720s 93.166us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.740s 16.496us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.190s 183.043us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.720s 71.125us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.630s 4.394ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.740s 16.496us 20 20 100.00
sram_ctrl_csr_aliasing 0.720s 71.125us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.094m 69.207ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.281m 54.427ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 34.451m 34.916ms 49 50 98.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.436m 13.485ms 50 50 100.00
V2 bijection sram_ctrl_bijection 45.667m 459.962ms 49 50 98.00
V2 access_during_key_req sram_ctrl_access_during_key_req 36.932m 20.630ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.797m 18.284ms 50 50 100.00
V2 executable sram_ctrl_executable 31.533m 22.517ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.722m 2.077ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.915m 48.824ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.674m 3.170ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.739m 6.523ms 50 50 100.00
V2 regwen sram_ctrl_regwen 27.014m 10.638ms 48 50 96.00
V2 ram_cfg sram_ctrl_ram_cfg 4.230s 3.748ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.862h 3.613s 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.710s 19.007us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.940s 158.286us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.940s 158.286us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.720s 93.166us 5 5 100.00
sram_ctrl_csr_rw 0.740s 16.496us 20 20 100.00
sram_ctrl_csr_aliasing 0.720s 71.125us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.860s 29.126us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.720s 93.166us 5 5 100.00
sram_ctrl_csr_rw 0.740s 16.496us 20 20 100.00
sram_ctrl_csr_aliasing 0.720s 71.125us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.860s 29.126us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 57.830s 117.427ms 19 20 95.00
V2S tl_intg_err sram_ctrl_sec_cm 3.200s 288.807us 5 5 100.00
sram_ctrl_tl_intg_err 2.510s 258.963us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.200s 288.807us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.510s 258.963us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 27.014m 10.638ms 48 50 96.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.740s 16.496us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 31.533m 22.517ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 31.533m 22.517ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 31.533m 22.517ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.797m 18.284ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 57.830s 117.427ms 19 20 95.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.633m 1.016ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.633m 1.016ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.633m 1.016ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 31.533m 22.517ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.200s 288.807us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.797m 18.284ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.200s 288.807us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.200s 288.807us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.633m 1.016ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.200s 288.807us 5 5 100.00
V2S TOTAL 44 45 97.78
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.755m 1.698ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1034 1040 99.42

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 12 75.00
V2S 3 3 2 66.67
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results