SRAM_CTRL/MAIN Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.954m	916.605us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	141.533us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	25.880us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.280s	121.499us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.780s	19.479us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.570s	367.535us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	25.880us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	19.479us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.782m	138.011ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.080m	5.531ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	35.280m	23.470ms	48	50	96.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.524m	5.800ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	49.955m	400.886ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	29.045m	63.040ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.821m	63.987ms	50	50	100.00
V2	executable	sram_ctrl_executable	36.133m	119.681ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.853m	2.019ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.767m	120.614ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.546m	5.826ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.925m	3.900ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	33.437m	43.954ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.260s	2.805ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.173h	517.265ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.720s	32.494us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.390s	157.637us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.390s	157.637us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	141.533us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	25.880us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	19.479us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	47.598us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	141.533us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	25.880us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	19.479us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	47.598us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.400m	117.660ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.030s	233.143us	5	5	100.00
		sram_ctrl_tl_intg_err	2.680s	284.403us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.030s	233.143us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.680s	284.403us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.437m	43.954ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	25.880us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	36.133m	119.681ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	36.133m	119.681ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	36.133m	119.681ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.821m	63.987ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.400m	117.660ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.954m	916.605us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.954m	916.605us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.954m	916.605us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	36.133m	119.681ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.030s	233.143us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.821m	63.987ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.030s	233.143us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.030s	233.143us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.954m	916.605us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.030s	233.143us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.898m	3.133ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_multiple_keys has 2 failures.
  - 1.sram_ctrl_multiple_keys.54019061335334859203707166101471605516244547408576296330552189933037070626262
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 27406441795 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x1c4a7e7b
  UVM_INFO @ 27406441795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.sram_ctrl_multiple_keys.68467192087899486982347579995473992735085325594329888611400895683299352987567
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 22891900232 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x99d17148
  UVM_INFO @ 22891900232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 44.sram_ctrl_bijection.46071228642088429017082926966566629715836435300508552194757999843317434534732
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.sram_ctrl_bijection.88513516535301758011469903879119178096421778776406430193699250229679864408422
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 39.sram_ctrl_stress_all.107487878848155715406609278185711435567310918132072528366463095730927603067393
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:e6a518a4-c1ec-4b98-a4b5-3c822677ef04
```

SRAM_CTRL/MAIN Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `2e5d86c9b5`