SRAM_CTRL/MAIN Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.701m	470.232us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	55.054us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	115.461us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.310s	1.536ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	50.308us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.990s	371.262us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	115.461us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	50.308us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.934m	82.778ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.984m	15.661ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	32.293m	8.499ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.231m	92.520ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	48.518m	344.857ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	52.863m	85.727ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.916m	62.765ms	50	50	100.00
V2	executable	sram_ctrl_executable	37.298m	132.001ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.934m	546.680us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.069m	24.371ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.483m	801.548us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	3.269m	3.403ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	39.224m	16.726ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.880s	1.299ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.578h	583.605ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.700s	22.770us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.530s	166.034us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.530s	166.034us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	55.054us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	115.461us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	50.308us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	25.828us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	55.054us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	115.461us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	50.308us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	25.828us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.118m	117.384ms	19	20	95.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.900s	3.097ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.520s	334.288us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.900s	3.097ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.520s	334.288us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	39.224m	16.726ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	115.461us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	37.298m	132.001ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	37.298m	132.001ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	37.298m	132.001ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.916m	62.765ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.118m	117.384ms	19	20	95.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.701m	470.232us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.701m	470.232us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.701m	470.232us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	37.298m	132.001ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.900s	3.097ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.916m	62.765ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.900s	3.097ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.900s	3.097ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.701m	470.232us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.900s	3.097ms	5	5	100.00
V2S		TOTAL			44	45	97.78
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.169m	3.172ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	2	66.67
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 11.sram_ctrl_stress_all.26191186026405926550321862387165851866405612730165451760931403409276289529514
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 2538168240884 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x4f6c2108
  UVM_INFO @ 2538168240884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 19.sram_ctrl_passthru_mem_tl_intg_err.105879049970580941235401380018271972378022504237760415364462639643198051074576
    Line 319, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 11106481510 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 11106481510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 20.sram_ctrl_stress_all.67227049625507620473123401840088919442227893867607325080014857619842469879669
    Line 294, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 2721837767544 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x6c4a022
  UVM_INFO @ 2721837767544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 46.sram_ctrl_bijection.67063365061684729774247735012214063972838433864893591240832545431593424861197
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 47.sram_ctrl_multiple_keys.17719472662405159472515754596133929413377092463762694930605000130278510593300
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 15548470465 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xd661c385
  UVM_INFO @ 15548470465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `6a84251492`