SRAM_CTRL/MAIN Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.426m 947.543us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.730s 141.864us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.730s 36.269us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.230s 588.330us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.780s 22.074us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.790s 3.866ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.730s 36.269us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 22.074us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.051m 21.662ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.012m 27.855ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 39.879m 41.842ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.511m 23.421ms 50 50 100.00
V2 bijection sram_ctrl_bijection 50.211m 459.684ms 49 50 98.00
V2 access_during_key_req sram_ctrl_access_during_key_req 33.693m 12.195ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.374m 78.266ms 50 50 100.00
V2 executable sram_ctrl_executable 35.943m 108.900ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.634m 2.762ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.947m 53.501ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.578m 820.280us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.650m 1.214ms 50 50 100.00
V2 regwen sram_ctrl_regwen 35.101m 23.405ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 3.840s 1.354ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.578h 573.596ms 48 50 96.00
V2 alert_test sram_ctrl_alert_test 0.740s 28.587us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.760s 450.992us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.760s 450.992us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.730s 141.864us 5 5 100.00
sram_ctrl_csr_rw 0.730s 36.269us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 22.074us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.880s 32.731us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.730s 141.864us 5 5 100.00
sram_ctrl_csr_rw 0.730s 36.269us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 22.074us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.880s 32.731us 20 20 100.00
V2 TOTAL 737 740 99.59
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 57.710s 29.455ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.380s 329.580us 5 5 100.00
sram_ctrl_tl_intg_err 2.800s 752.975us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.380s 329.580us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.800s 752.975us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 35.101m 23.405ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.730s 36.269us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 35.943m 108.900ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 35.943m 108.900ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 35.943m 108.900ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.374m 78.266ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 57.710s 29.455ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.426m 947.543us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.426m 947.543us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.426m 947.543us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 35.943m 108.900ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.380s 329.580us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.374m 78.266ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.380s 329.580us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.380s 329.580us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.426m 947.543us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.380s 329.580us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.116m 9.042ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1037 1040 99.71

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results