SRAM_CTRL/MAIN Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: edf2fd5092

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 1.729m 1.843ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.710s 13.089us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.700s 89.158us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.180s 179.381us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.750s 18.370us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.950s 2.503ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.700s 89.158us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 18.370us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.020m 72.037ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.038m 25.223ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 29.851m 25.119ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.327m 14.358ms 50 50 100.00
V2 bijection sram_ctrl_bijection 49.733m 176.041ms 48 50 96.00
V2 access_during_key_req sram_ctrl_access_during_key_req 34.933m 80.843ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.283m 179.782ms 50 50 100.00
V2 executable sram_ctrl_executable 38.958m 48.424ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.469m 13.828ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.610m 45.559ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.563m 5.093ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.358m 3.248ms 50 50 100.00
V2 regwen sram_ctrl_regwen 36.151m 4.730ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 5.400s 6.698ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.826h 360.023ms 48 50 96.00
V2 alert_test sram_ctrl_alert_test 0.710s 45.721us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.650s 362.086us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.650s 362.086us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.710s 13.089us 5 5 100.00
sram_ctrl_csr_rw 0.700s 89.158us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 18.370us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 24.032us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.710s 13.089us 5 5 100.00
sram_ctrl_csr_rw 0.700s 89.158us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 18.370us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 24.032us 20 20 100.00
V2 TOTAL 736 740 99.46
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 52.480s 7.510ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.530s 1.390ms 5 5 100.00
sram_ctrl_tl_intg_err 3.530s 790.842us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.530s 1.390ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.530s 790.842us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 36.151m 4.730ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.700s 89.158us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 38.958m 48.424ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 38.958m 48.424ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 38.958m 48.424ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.283m 179.782ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 52.480s 7.510ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 1.729m 1.843ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 1.729m 1.843ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 1.729m 1.843ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 38.958m 48.424ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.530s 1.390ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.283m 179.782ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.530s 1.390ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.530s 1.390ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 1.729m 1.843ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.530s 1.390ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 4.131m 5.201ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1036 1040 99.62

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results