SRAM_CTRL/MAIN Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.895m 1.335ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.690s 75.571us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 14.695us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.160s 416.578us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.730s 20.448us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.090s 3.197ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 14.695us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 20.448us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.095m 20.682ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.089m 54.690ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 42.400m 35.881ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.648m 39.049ms 50 50 100.00
V2 bijection sram_ctrl_bijection 46.551m 962.500ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 30.638m 31.903ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.937m 20.404ms 50 50 100.00
V2 executable sram_ctrl_executable 31.923m 26.325ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.859m 1.019ms 50 50 100.00
sram_ctrl_partial_access_b2b 11.190m 28.657ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.668m 10.874ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 3.109m 2.793ms 50 50 100.00
V2 regwen sram_ctrl_regwen 40.937m 17.591ms 49 50 98.00
V2 ram_cfg sram_ctrl_ram_cfg 4.610s 4.204ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.550h 1.567s 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.730s 14.603us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.950s 600.097us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.950s 600.097us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.690s 75.571us 5 5 100.00
sram_ctrl_csr_rw 0.720s 14.695us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 20.448us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 212.449us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.690s 75.571us 5 5 100.00
sram_ctrl_csr_rw 0.720s 14.695us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 20.448us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 212.449us 20 20 100.00
V2 TOTAL 738 740 99.73
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 56.870s 29.425ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.420s 644.238us 5 5 100.00
sram_ctrl_tl_intg_err 2.830s 1.446ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.420s 644.238us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.830s 1.446ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 40.937m 17.591ms 49 50 98.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 14.695us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 31.923m 26.325ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 31.923m 26.325ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 31.923m 26.325ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.937m 20.404ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 56.870s 29.425ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.895m 1.335ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.895m 1.335ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.895m 1.335ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 31.923m 26.325ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.420s 644.238us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.937m 20.404ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.420s 644.238us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.420s 644.238us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.895m 1.335ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.420s 644.238us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 6.323m 17.823ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 1037 1040 99.71

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results