SRAM_CTRL/MAIN Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.669m	1.619ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	25.093us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.770s	165.364us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.450s	681.389us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	84.968us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.850s	374.882us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.770s	165.364us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	84.968us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.475m	41.371ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.163m	6.081ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	34.286m	30.349ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.437m	16.081ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	50.854m	179.606ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	41.017m	24.167ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.699m	61.242ms	50	50	100.00
V2	executable	sram_ctrl_executable	30.110m	27.145ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.735m	3.927ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.450m	42.902ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.631m	767.878us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.714m	3.137ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	40.983m	26.361ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.120s	4.778ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.700h	3.094s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.720s	14.696us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.570s	156.976us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.570s	156.976us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	25.093us	5	5	100.00
		sram_ctrl_csr_rw	0.770s	165.364us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	84.968us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	77.793us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	25.093us	5	5	100.00
		sram_ctrl_csr_rw	0.770s	165.364us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	84.968us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	77.793us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.233m	140.689ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.160s	750.836us	5	5	100.00
		sram_ctrl_tl_intg_err	2.560s	871.475us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.160s	750.836us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.560s	871.475us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	40.983m	26.361ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.770s	165.364us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.110m	27.145ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.110m	27.145ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.110m	27.145ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.699m	61.242ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.233m	140.689ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.669m	1.619ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.669m	1.619ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.669m	1.619ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.110m	27.145ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.160s	750.836us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.699m	61.242ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.160s	750.836us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.160s	750.836us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.669m	1.619ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.160s	750.836us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.865m	11.730ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1039	1040	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test sram_ctrl_bijection has 1 failures.

    • 19.sram_ctrl_bijection.76775637514292875511207922732399806595743112261930282745993579310346608898556
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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