SRAM_CTRL/MAIN Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.697m	5.546ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	18.707us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	210.475us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.280s	289.638us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	17.299us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.330s	1.417ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	210.475us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	17.299us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.033m	76.607ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.086m	34.907ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	30.130m	172.425ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.408m	7.781ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	54.286m	689.417ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	32.909m	75.360ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.989m	75.353ms	50	50	100.00
V2	executable	sram_ctrl_executable	38.480m	8.364ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.536m	3.289ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.006m	9.570ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.800m	818.949us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.885m	1.596ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	33.187m	16.946ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.780s	5.589ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.316h	329.200ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.780s	140.736us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.610s	286.384us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.610s	286.384us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	18.707us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	210.475us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	17.299us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	28.088us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	18.707us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	210.475us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	17.299us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	28.088us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.117m	117.280ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.550s	974.265us	5	5	100.00
		sram_ctrl_tl_intg_err	2.700s	322.661us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.550s	974.265us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.700s	322.661us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.187m	16.946ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	210.475us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	38.480m	8.364ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	38.480m	8.364ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	38.480m	8.364ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.989m	75.353ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.117m	117.280ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.697m	5.546ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.697m	5.546ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.697m	5.546ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	38.480m	8.364ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.550s	974.265us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.989m	75.353ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.550s	974.265us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.550s	974.265us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.697m	5.546ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.550s	974.265us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.296m	1.303ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1038	1040	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 5.sram_ctrl_bijection.53723004321542669904101202317961121914237357568966514258352069673792700172727
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_multiple_keys has 1 failures.

    • 25.sram_ctrl_multiple_keys.115495516429677742831877157873492203577935392665635412991052155117591422736622
      Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 21000893081 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xfc3d32
        UVM_INFO @ 21000893081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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