SRAM_CTRL/MAIN Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.353m 1.583ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.750s 31.366us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 27.211us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.780s 41.269us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 197.275us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.820s 2.047ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 27.211us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 197.275us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.430m 159.046ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.418m 111.131ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 34.785m 291.503ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.892m 88.785ms 50 50 100.00
V2 bijection sram_ctrl_bijection 49.726m 177.856ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 32.661m 378.798ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.977m 73.945ms 50 50 100.00
V2 executable sram_ctrl_executable 32.443m 14.209ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 3.083m 6.470ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.174m 19.230ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.496m 1.597ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.747m 1.604ms 50 50 100.00
V2 regwen sram_ctrl_regwen 33.729m 79.163ms 49 50 98.00
V2 ram_cfg sram_ctrl_ram_cfg 4.760s 4.202ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.315h 1.559s 47 50 94.00
V2 alert_test sram_ctrl_alert_test 0.740s 40.154us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.280s 135.635us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.280s 135.635us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.750s 31.366us 5 5 100.00
sram_ctrl_csr_rw 0.720s 27.211us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 197.275us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 31.720us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.750s 31.366us 5 5 100.00
sram_ctrl_csr_rw 0.720s 27.211us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 197.275us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 31.720us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.202m 64.171ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.420s 508.732us 5 5 100.00
sram_ctrl_tl_intg_err 2.560s 988.248us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.420s 508.732us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.560s 988.248us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 33.729m 79.163ms 49 50 98.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 27.211us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 32.443m 14.209ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 32.443m 14.209ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 32.443m 14.209ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.977m 73.945ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.202m 64.171ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.353m 1.583ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.353m 1.583ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.353m 1.583ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 32.443m 14.209ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.420s 508.732us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.977m 73.945ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.420s 508.732us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.420s 508.732us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.353m 1.583ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.420s 508.732us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.965m 1.774ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1035 1040 99.52

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.99 99.19 94.27 99.72 100.00 96.03 99.12 97.62

Failure Buckets

Past Results