SRAM_CTRL/MAIN Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.497m	5.244ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	21.013us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	40.018us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.310s	633.728us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	62.407us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.420s	1.444ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	40.018us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	62.407us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.284m	86.241ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.112m	23.174ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	43.441m	90.775ms	48	50	96.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.311m	80.452ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	48.131m	689.468ms	47	50	94.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	31.526m	21.589ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.716m	113.566ms	50	50	100.00
V2	executable	sram_ctrl_executable	27.856m	71.933ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.423m	5.330ms	50	50	100.00
		sram_ctrl_partial_access_b2b	12.294m	457.928ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.629m	801.716us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.507m	1.815ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	29.683m	101.107ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.200s	3.339ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.609h	399.819ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.710s	16.151us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.150s	173.458us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.150s	173.458us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	21.013us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	40.018us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	62.407us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	75.501us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	21.013us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	40.018us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	62.407us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	75.501us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.006m	88.078ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.530s	2.464ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.020s	560.622us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.530s	2.464ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.020s	560.622us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	29.683m	101.107ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	40.018us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	27.856m	71.933ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	27.856m	71.933ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	27.856m	71.933ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.716m	113.566ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.006m	88.078ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.497m	5.244ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.497m	5.244ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.497m	5.244ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	27.856m	71.933ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.530s	2.464ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.716m	113.566ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.530s	2.464ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.530s	2.464ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.497m	5.244ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.530s	2.464ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.511m	2.538ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1033	1040	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test sram_ctrl_bijection has 3 failures.
  - 7.sram_ctrl_bijection.96260665850297629506598260489179222099981235197408564174459153569048420440700
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.sram_ctrl_bijection.29171683940678329715033402848753227089089005509398146233609881585066983295376
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_multiple_keys has 2 failures.
  - 8.sram_ctrl_multiple_keys.70603944475279858668068982180690593412858775037077059708508343316475793111926
    Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 57821786858 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x59af220f
  UVM_INFO @ 57821786858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.sram_ctrl_multiple_keys.92968723889658765639220296079081107659756905326129294049620752165318314981576
    Line 296, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 155744899723 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x1b75ecac
  UVM_INFO @ 155744899723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:825) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 12.sram_ctrl_stress_all_with_rand_reset.35943778325497896981563216454650587755664951714144712484022785724576858629230
    Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6323815790 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6323815790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 26.sram_ctrl_regwen.28912731554060510900732881890720607382650952485010620874136222677279465439439
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 15537369453 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x24349c91
  UVM_INFO @ 15537369453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `aad711e1bc`