SRAM_CTRL/MAIN Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.628m	5.579ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	23.082us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	18.639us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.300s	1.927ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.710s	21.858us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.280s	922.922us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	18.639us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	21.858us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.197m	125.654ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.238m	23.867ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	33.828m	110.609ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.381m	28.071ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	46.791m	155.926ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	29.147m	88.073ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.948m	20.531ms	50	50	100.00
V2	executable	sram_ctrl_executable	34.742m	29.881ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.669m	1.432ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.158m	106.177ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.575m	810.828us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.695m	787.162us	50	50	100.00
V2	regwen	sram_ctrl_regwen	25.831m	23.479ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.440s	6.664ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.910h	949.141ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.730s	56.530us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.630s	142.086us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.630s	142.086us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	23.082us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	18.639us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	21.858us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.780s	83.910us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	23.082us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	18.639us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	21.858us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.780s	83.910us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	58.450s	50.321ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.100s	676.189us	5	5	100.00
		sram_ctrl_tl_intg_err	2.360s	620.404us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.100s	676.189us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.360s	620.404us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	25.831m	23.479ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	18.639us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	34.742m	29.881ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	34.742m	29.881ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	34.742m	29.881ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.948m	20.531ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	58.450s	50.321ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.628m	5.579ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.628m	5.579ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.628m	5.579ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	34.742m	29.881ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.100s	676.189us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.948m	20.531ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.100s	676.189us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.100s	676.189us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.628m	5.579ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.100s	676.189us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.497m	9.124ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1038	1040	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_regwen has 1 failures.

    • 36.sram_ctrl_regwen.114257747322733627352706786262885625399140072214814766527376036910067410867839
      Line 288, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_regwen/latest/run.log

        UVM_FATAL @ 59359563909 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x1af4f374
        UVM_INFO @ 59359563909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_multiple_keys has 1 failures.

    • 43.sram_ctrl_multiple_keys.83193733069751116889246142654140960483906922253300529519927105555243020042675
      Line 294, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 130841399363 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x35b9cbb1
        UVM_INFO @ 130841399363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.17_09.47.33
• 2024.07.16_09.54.35
• 2024.07.15_09.42.17
• 2024.07.14_08.57.57
• 2024.07.13_08.35.39
• 2024.07.12_09.24.27
• 2024.07.11_10.47.53