SRAM_CTRL/MAIN Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.425m	2.001ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	28.569us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	15.377us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.320s	306.222us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.820s	16.462us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.610s	389.681us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	15.377us	20	20	100.00
		sram_ctrl_csr_aliasing	0.820s	16.462us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.207m	42.239ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.223m	44.580ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	27.439m	53.227ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.769m	10.264ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	45.828m	317.208ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	27.715m	16.430ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.713m	73.991ms	50	50	100.00
V2	executable	sram_ctrl_executable	31.144m	112.491ms	48	50	96.00
V2	partial_access	sram_ctrl_partial_access	2.570m	2.582ms	50	50	100.00
		sram_ctrl_partial_access_b2b	12.196m	117.904ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.784m	800.224us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	3.112m	3.129ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	33.656m	66.638ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.140s	5.595ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.819h	698.214ms	47	50	94.00
V2	alert_test	sram_ctrl_alert_test	0.740s	22.275us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.660s	514.775us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.660s	514.775us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	28.569us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	15.377us	20	20	100.00
		sram_ctrl_csr_aliasing	0.820s	16.462us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	33.256us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	28.569us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	15.377us	20	20	100.00
		sram_ctrl_csr_aliasing	0.820s	16.462us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	33.256us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.029m	37.141ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.200s	384.497us	5	5	100.00
		sram_ctrl_tl_intg_err	2.450s	949.056us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.200s	384.497us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.450s	949.056us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.656m	66.638ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	15.377us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	31.144m	112.491ms	48	50	96.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	31.144m	112.491ms	48	50	96.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	31.144m	112.491ms	48	50	96.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.713m	73.991ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.029m	37.141ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.425m	2.001ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.425m	2.001ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.425m	2.001ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	31.144m	112.491ms	48	50	96.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.200s	384.497us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.713m	73.991ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.200s	384.497us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.200s	384.497us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.425m	2.001ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.200s	384.497us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.147m	1.695ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1030	1040	99.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_executable has 2 failures.
  - 4.sram_ctrl_executable.18289232534468483021229221416259333190788315771292389177181288228838026628137
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 23166571105 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xf25ff92d
  UVM_INFO @ 23166571105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.sram_ctrl_executable.57632285387821076931494578643275922601032028913634176058944352047363598316647
    Line 320, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 257906211628 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x6fe23651
  UVM_INFO @ 257906211628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 8.sram_ctrl_bijection.68095028476403004503427976122509438482238086116513190499616713606127615597215
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.sram_ctrl_bijection.7023929083078017790529171535722266260489998097167939861712060441511850856392
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:839) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 2 failures.
  - 22.sram_ctrl_stress_all_with_rand_reset.45954576716347648317394896708809773053744181617572016196694038999810598281078
    Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1464230281 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1464230281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.sram_ctrl_stress_all_with_rand_reset.7330943981511930964263700146582303130814431334374923572729848781693117912100
    Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3696609531 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3696609531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

22.sram_ctrl_stress_all.115179151077354289974603455731769965181697384429734543186620890657880191473609
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 2368892514 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 2368892514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.sram_ctrl_stress_all.104460000862857373925461859584037166807399243734952233806308566930197611037537
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 393530831 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 393530831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 46.sram_ctrl_multiple_keys.4036435631023003739104400228757037516233537495443484764619466385482390235741
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 23162851786 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xd31febc
  UVM_INFO @ 23162851786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 1 failures.
  - 47.sram_ctrl_stress_all.39712872094013698686876785325361572836355250467143243912135101318621754606168
    Line 324, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 228483588084 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x5450fce7
  UVM_INFO @ 228483588084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```