SRAM_CTRL/MAIN Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.669m 5.512ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.690s 52.007us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 22.666us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.900s 42.165us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.770s 37.778us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.510s 1.202ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 22.666us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 37.778us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.582m 256.500ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.132m 65.476ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 42.684m 13.223ms 48 50 96.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.829m 5.927ms 50 50 100.00
V2 bijection sram_ctrl_bijection 51.673m 717.798ms 49 50 98.00
V2 access_during_key_req sram_ctrl_access_during_key_req 33.599m 35.575ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.865m 307.779ms 50 50 100.00
V2 executable sram_ctrl_executable 39.444m 110.659ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.927m 1.091ms 50 50 100.00
sram_ctrl_partial_access_b2b 11.627m 68.509ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.442m 1.418ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.637m 819.385us 50 50 100.00
V2 regwen sram_ctrl_regwen 28.562m 41.966ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.710s 3.751ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.212h 386.507ms 48 50 96.00
V2 alert_test sram_ctrl_alert_test 0.720s 17.916us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.940s 319.659us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.940s 319.659us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.690s 52.007us 5 5 100.00
sram_ctrl_csr_rw 0.720s 22.666us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 37.778us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.840s 42.655us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.690s 52.007us 5 5 100.00
sram_ctrl_csr_rw 0.720s 22.666us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 37.778us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.840s 42.655us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.185m 54.226ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.330s 296.754us 5 5 100.00
sram_ctrl_tl_intg_err 2.790s 622.427us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.330s 296.754us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.790s 622.427us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 28.562m 41.966ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 22.666us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 39.444m 110.659ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 39.444m 110.659ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 39.444m 110.659ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.865m 307.779ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.185m 54.226ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.669m 5.512ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.669m 5.512ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.669m 5.512ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 39.444m 110.659ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.330s 296.754us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.865m 307.779ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.330s 296.754us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.330s 296.754us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.669m 5.512ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.330s 296.754us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 4.545m 10.883ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1035 1040 99.52

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results