SRAM_CTRL/MAIN Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 0 50 0.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.690s 41.438us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 46.201us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.250s 301.376us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.740s 16.528us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.840s 1.415ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 46.201us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 16.528us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 0 50 0.00
V1 mem_partial_access sram_ctrl_mem_partial_access 0 50 0.00
V1 TOTAL 55 205 26.83
V2 multiple_keys sram_ctrl_multiple_keys 0 50 0.00
V2 stress_pipeline sram_ctrl_stress_pipeline 0 50 0.00
V2 bijection sram_ctrl_bijection 0 50 0.00
V2 access_during_key_req sram_ctrl_access_during_key_req 0 50 0.00
V2 lc_escalation sram_ctrl_lc_escalation 0 50 0.00
V2 executable sram_ctrl_executable 0 50 0.00
V2 partial_access sram_ctrl_partial_access 0 50 0.00
sram_ctrl_partial_access_b2b 0 50 0.00
V2 max_throughput sram_ctrl_max_throughput 0 50 0.00
sram_ctrl_throughput_w_partial_write 0 50 0.00
V2 regwen sram_ctrl_regwen 0 50 0.00
V2 ram_cfg sram_ctrl_ram_cfg 0 50 0.00
V2 stress_all sram_ctrl_stress_all 0 50 0.00
V2 alert_test sram_ctrl_alert_test 0 50 0.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.700s 281.732us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.700s 281.732us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.690s 41.438us 5 5 100.00
sram_ctrl_csr_rw 0.720s 46.201us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 16.528us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 84.594us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.690s 41.438us 5 5 100.00
sram_ctrl_csr_rw 0.720s 46.201us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 16.528us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 84.594us 20 20 100.00
V2 TOTAL 40 740 5.41
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 56.760s 7.287ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 0 5 0.00
sram_ctrl_tl_intg_err 2.530s 309.737us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 0 5 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.530s 309.737us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 0 50 0.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 46.201us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 0 50 0.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 0 50 0.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 0 50 0.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 0 50 0.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 56.760s 7.287ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 0 50 0.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 0 50 0.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 0 50 0.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 0 50 0.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 0 5 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 0 50 0.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 0 5 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 0 5 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 0 50 0.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 0 5 0.00
V2S TOTAL 40 45 88.89
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 135 1040 12.98

Testplan Progress

Items Total Written Passing Progress
V1 8 8 5 62.50
V2 16 16 2 12.50
V2S 3 3 2 66.67
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
46.89 25.31 31.86 68.11 0.00 27.34 98.47 77.15

Failure Buckets

Past Results