SRAM_CTRL/MAIN Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.132m	1.345ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	126.949us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	43.344us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.350s	181.361us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	20.029us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.710s	356.022us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	43.344us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	20.029us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.646m	137.777ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.982m	10.246ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	32.028m	28.385ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.678m	6.305ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	51.639m	689.508ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	37.889m	18.521ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.779m	19.587ms	50	50	100.00
V2	executable	sram_ctrl_executable	36.623m	111.528ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.609m	2.108ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.137m	21.107ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.808m	808.535us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.577m	3.125ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	35.216m	5.014ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.770s	4.818ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.856h	63.322ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.720s	17.777us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.840s	561.803us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.840s	561.803us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	126.949us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	43.344us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	20.029us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	65.767us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	126.949us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	43.344us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	20.029us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	65.767us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	56.510s	27.135ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.220s	1.723ms	5	5	100.00
		sram_ctrl_tl_intg_err	7.140s	7.715ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.220s	1.723ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	7.140s	7.715ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	35.216m	5.014ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	43.344us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	36.623m	111.528ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	36.623m	111.528ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	36.623m	111.528ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.779m	19.587ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	56.510s	27.135ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.132m	1.345ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.132m	1.345ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.132m	1.345ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	36.623m	111.528ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.220s	1.723ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.779m	19.587ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.220s	1.723ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.220s	1.723ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.132m	1.345ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.220s	1.723ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.731m	5.750ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1037	1040	99.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 16.sram_ctrl_stress_all.28096136309656432737408598030982956415789937389818555810915244000843069731379
      Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 1867613822737 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x1da47e7d
        UVM_INFO @ 1867613822737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_executable has 1 failures.

    • 28.sram_ctrl_executable.91598910650797735550828203891643770193862205832943692416902916881609002040452
      Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 40645765046 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x55dda5b9
        UVM_INFO @ 40645765046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 44.sram_ctrl_stress_all.95315274839791887256571582411302148910755166175841236687838519408219856773662
      Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 54995014243 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xe878e110
        UVM_INFO @ 54995014243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.15_05.42.57
• 2024.08.14_08.47.13
• 2024.08.13_08.12.51
• 2024.08.12_08.41.59
• 2024.08.11_08.27.52
• 2024.08.10_08.34.00
• 2024.08.09_08.03.48