76588857da| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 3.044m | 1.620ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.760s | 21.964us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.770s | 15.756us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.330s | 596.351us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.760s | 50.358us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 6.100s | 5.000ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.770s | 15.756us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.760s | 50.358us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 6.356m | 90.113ms | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 3.038m | 5.007ms | 50 | 50 | 100.00 |
| V1 | TOTAL | 205 | 205 | 100.00 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 35.861m | 55.058ms | 50 | 50 | 100.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 7.776m | 25.706ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 52.231m | 749.489ms | 49 | 50 | 98.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 35.562m | 80.920ms | 50 | 50 | 100.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 2.606m | 228.628ms | 50 | 50 | 100.00 |
| V2 | executable | sram_ctrl_executable | 35.726m | 90.945ms | 50 | 50 | 100.00 |
| V2 | partial_access | sram_ctrl_partial_access | 2.781m | 4.261ms | 49 | 50 | 98.00 |
| sram_ctrl_partial_access_b2b | 10.395m | 27.429ms | 50 | 50 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 2.687m | 884.288us | 50 | 50 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 3.062m | 1.634ms | 50 | 50 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 33.082m | 17.664ms | 49 | 50 | 98.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 4.860s | 5.575ms | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 2.766h | 1.571s | 49 | 50 | 98.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.720s | 16.827us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.920s | 869.650us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.920s | 869.650us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.760s | 21.964us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.770s | 15.756us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.760s | 50.358us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.820s | 31.470us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.760s | 21.964us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.770s | 15.756us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.760s | 50.358us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.820s | 31.470us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 736 | 740 | 99.46 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 57.390s | 35.448ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 3.250s | 468.500us | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 2.630s | 184.526us | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 3.250s | 468.500us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.630s | 184.526us | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 33.082m | 17.664ms | 49 | 50 | 98.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.770s | 15.756us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 35.726m | 90.945ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 35.726m | 90.945ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 35.726m | 90.945ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 2.606m | 228.628ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 57.390s | 35.448ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_readback | sram_ctrl_smoke | 3.044m | 1.620ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 3.044m | 1.620ms | 50 | 50 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 3.044m | 1.620ms | 50 | 50 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 35.726m | 90.945ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 3.250s | 468.500us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 2.606m | 228.628ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 3.250s | 468.500us | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 3.250s | 468.500us | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 3.044m | 1.620ms | 50 | 50 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 3.250s | 468.500us | 5 | 5 | 100.00 |
| V2S | TOTAL | 45 | 45 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 3.771m | 3.256ms | 48 | 50 | 96.00 |
| V3 | TOTAL | 48 | 50 | 96.00 | |||
| TOTAL | 1034 | 1040 | 99.42 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 16 | 16 | 12 | 75.00 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.94 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.26 |
UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
17.sram_ctrl_stress_all_with_rand_reset.114864034933829549815379372474442187022729076875572058386545035710258084334762
Line 299, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6283748714 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6283748714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.sram_ctrl_stress_all_with_rand_reset.78031661228835777052961089527513628350126105814873636453963372505496586894363
Line 340, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7616911763 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7616911763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
5.sram_ctrl_bijection.81248297057529939335997734976084169520154346289080445559134588108489939847503
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_bijection/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 1 failures:
24.sram_ctrl_stress_all.65075471524715910288173442739011506618362169492578085159012839274391715324058
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 411247789 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 411247789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
40.sram_ctrl_partial_access.105736437067505416546943783069433702079080236127204840761460936831445321793558
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access/latest/run.log
UVM_FATAL @ 15534452796 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x6ec9c89b
UVM_INFO @ 15534452796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
41.sram_ctrl_regwen.87422098978293393110911317040495230861202148933737601566025046532997532804002
Line 309, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_regwen/latest/run.log
UVM_FATAL @ 97482446844 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x3bb88929
UVM_INFO @ 97482446844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---