SRAM_CTRL/MAIN Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.498m 1.347ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.700s 18.536us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.730s 67.843us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.150s 126.177us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 23.882us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.200s 1.453ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.730s 67.843us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 23.882us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 6.208m 81.677ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 3.010m 22.819ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 30.899m 75.960ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.708m 20.383ms 50 50 100.00
V2 bijection sram_ctrl_bijection 46.999m 179.837ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 34.838m 78.042ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.758m 32.336ms 50 50 100.00
V2 executable sram_ctrl_executable 39.356m 24.415ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.517m 1.333ms 50 50 100.00
sram_ctrl_partial_access_b2b 11.737m 32.451ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.712m 6.363ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.689m 3.396ms 50 50 100.00
V2 regwen sram_ctrl_regwen 32.102m 84.655ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.010s 1.344ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.887h 572.131ms 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.720s 50.259us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.440s 865.691us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.440s 865.691us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.700s 18.536us 5 5 100.00
sram_ctrl_csr_rw 0.730s 67.843us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 23.882us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.920s 208.579us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.700s 18.536us 5 5 100.00
sram_ctrl_csr_rw 0.730s 67.843us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 23.882us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.920s 208.579us 20 20 100.00
V2 TOTAL 739 740 99.86
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 57.390s 28.149ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.300s 839.425us 5 5 100.00
sram_ctrl_tl_intg_err 3.440s 971.772us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.300s 839.425us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.440s 971.772us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 32.102m 84.655ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.730s 67.843us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 39.356m 24.415ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 39.356m 24.415ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 39.356m 24.415ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.758m 32.336ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 57.390s 28.149ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.498m 1.347ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.498m 1.347ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.498m 1.347ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 39.356m 24.415ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.300s 839.425us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.758m 32.336ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.300s 839.425us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.300s 839.425us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.498m 1.347ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.300s 839.425us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.657m 1.785ms 48 50 96.00
V3 TOTAL 48 50 96.00
TOTAL 1037 1040 99.71

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44

Failure Buckets

Past Results