SRAM_CTRL/MAIN Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.725m	8.533ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.720s	25.685us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	13.885us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.210s	623.472us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.780s	21.382us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.870s	1.417ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	13.885us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	21.382us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.284m	43.084ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.237m	20.086ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	32.634m	46.233ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.803m	119.358ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	45.853m	167.207ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	25.837m	80.487ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.832m	32.261ms	50	50	100.00
V2	executable	sram_ctrl_executable	38.896m	56.306ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.711m	1.054ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.765m	116.108ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.839m	7.575ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.788m	1.614ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	29.574m	22.993ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.860s	5.579ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.442h	187.030ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.700s	37.635us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.560s	161.000us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.560s	161.000us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.720s	25.685us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	13.885us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	21.382us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.900s	94.522us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.720s	25.685us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	13.885us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	21.382us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.900s	94.522us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	59.320s	14.680ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.970s	865.173us	5	5	100.00
		sram_ctrl_tl_intg_err	2.790s	5.118ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.970s	865.173us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.790s	5.118ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	29.574m	22.993ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	13.885us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	38.896m	56.306ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	38.896m	56.306ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	38.896m	56.306ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.832m	32.261ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	59.320s	14.680ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.725m	8.533ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.725m	8.533ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.725m	8.533ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	38.896m	56.306ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.970s	865.173us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.832m	32.261ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.970s	865.173us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.970s	865.173us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.725m	8.533ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.970s	865.173us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.727m	1.923ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1034	1040	99.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 2 failures.
  - 1.sram_ctrl_stress_all_with_rand_reset.101617787327014534499649599225647121883980767621993608296192730747735562660553
    Line 304, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2353861538 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2353861538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.sram_ctrl_stress_all_with_rand_reset.17024436441416602124181968709536337216248687539871957855548040381947682961428
    Line 308, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1439860076 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1439860076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 18.sram_ctrl_bijection.20460799133108652513087766640967976907544194866182578767259625620248290821474
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.sram_ctrl_bijection.48596391195788065441302171271462565842303607745918497238547944707649948764380
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 27.sram_ctrl_executable.34499868984975908607762430203035142941216558002449405324833577605412186049933
    Line 310, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 195107514650 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xd3cdb443
  UVM_INFO @ 195107514650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 27.sram_ctrl_regwen.109074155160280443908883792835266230442053906733944676303536664568602679289255
    Line 312, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 106869117166 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x3a715f7b
  UVM_INFO @ 106869117166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `f1535c5540`