e45ccd274a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 2.897m | 966.259us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.690s | 20.199us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.740s | 51.452us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 1.780s | 88.156us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.830s | 65.249us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 4.910s | 431.025us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.740s | 51.452us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.830s | 65.249us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 6.853m | 413.169ms | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 3.216m | 97.968ms | 50 | 50 | 100.00 |
| V1 | TOTAL | 205 | 205 | 100.00 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 30.152m | 134.669ms | 49 | 50 | 98.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 6.465m | 47.202ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 47.276m | 637.070ms | 49 | 50 | 98.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 30.786m | 16.410ms | 50 | 50 | 100.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 1.708m | 103.666ms | 50 | 50 | 100.00 |
| V2 | executable | sram_ctrl_executable | 28.513m | 45.159ms | 49 | 50 | 98.00 |
| V2 | partial_access | sram_ctrl_partial_access | 2.367m | 5.516ms | 50 | 50 | 100.00 |
| sram_ctrl_partial_access_b2b | 11.943m | 160.525ms | 50 | 50 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 2.855m | 903.605us | 50 | 50 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 2.997m | 4.115ms | 50 | 50 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 33.970m | 22.582ms | 49 | 50 | 98.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 4.160s | 4.813ms | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 2.004h | 444.443ms | 49 | 50 | 98.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.740s | 173.875us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 5.030s | 1.014ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 5.030s | 1.014ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.690s | 20.199us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.740s | 51.452us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.830s | 65.249us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.810s | 41.289us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.690s | 20.199us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.740s | 51.452us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.830s | 65.249us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.810s | 41.289us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 735 | 740 | 99.32 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 1.192m | 64.026ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 3.630s | 1.400ms | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 2.540s | 184.806us | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 3.630s | 1.400ms | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.540s | 184.806us | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 33.970m | 22.582ms | 49 | 50 | 98.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.740s | 51.452us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 28.513m | 45.159ms | 49 | 50 | 98.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 28.513m | 45.159ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 28.513m | 45.159ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 1.708m | 103.666ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 1.192m | 64.026ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_readback | sram_ctrl_smoke | 2.897m | 966.259us | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.897m | 966.259us | 50 | 50 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.897m | 966.259us | 50 | 50 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 28.513m | 45.159ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 3.630s | 1.400ms | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 1.708m | 103.666ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 3.630s | 1.400ms | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 3.630s | 1.400ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.897m | 966.259us | 50 | 50 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 3.630s | 1.400ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 45 | 45 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 3.546m | 14.378ms | 50 | 50 | 100.00 |
| V3 | TOTAL | 50 | 50 | 100.00 | |||
| TOTAL | 1035 | 1040 | 99.52 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 16 | 16 | 11 | 68.75 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 1 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.97 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.44 |
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
21.sram_ctrl_executable.101828780691014951887122345710336446321726469136589221513767834991163738063656
Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_executable/latest/run.log
UVM_FATAL @ 100994320314 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x635ace78
UVM_INFO @ 100994320314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
22.sram_ctrl_bijection.74949565563865987890893206064248932854921518931837136423367567850606561706257
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_bijection/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
28.sram_ctrl_regwen.69130540916391859666252276758893153589579809700825327327847585585333163055794
Line 307, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_regwen/latest/run.log
UVM_FATAL @ 102875284362 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x21e71563
UVM_INFO @ 102875284362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
41.sram_ctrl_multiple_keys.49572169832261707172355653091544611099224391858613397744140075818843925210406
Line 300, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_multiple_keys/latest/run.log
UVM_FATAL @ 161143046716 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x4f4ad53c
UVM_INFO @ 161143046716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 1 failures:
43.sram_ctrl_stress_all.72540419736575921959112519314095733947103476240320231684168849987603003025866
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 2467527561 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 2467527561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---