SRAM_CTRL/MAIN Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.216m	465.320us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.790s	46.013us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.800s	19.445us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.030s	1.119ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.860s	16.224us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.340s	1.280ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.800s	19.445us	20	20	100.00
		sram_ctrl_csr_aliasing	0.860s	16.224us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.508m	82.753ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.841m	37.809ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	22.387m	110.696ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.852m	6.247ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	47.735m	426.132ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	32.558m	48.064ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.952m	62.473ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.282m	26.260ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	1.533m	1.292ms	50	50	100.00
		sram_ctrl_partial_access_b2b	12.934m	99.397ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.799m	3.320ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.477m	1.568ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	29.365m	14.742ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.780s	2.252ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.304h	723.178ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.090s	13.183us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.830s	525.958us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.830s	525.958us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.790s	46.013us	5	5	100.00
		sram_ctrl_csr_rw	0.800s	19.445us	20	20	100.00
		sram_ctrl_csr_aliasing	0.860s	16.224us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.940s	31.585us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.790s	46.013us	5	5	100.00
		sram_ctrl_csr_rw	0.800s	19.445us	20	20	100.00
		sram_ctrl_csr_aliasing	0.860s	16.224us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.940s	31.585us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.367m	50.354ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.880s	544.279us	5	5	100.00
		sram_ctrl_tl_intg_err	2.500s	280.146us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.880s	544.279us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.500s	280.146us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	29.365m	14.742ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.800s	19.445us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.282m	26.260ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.282m	26.260ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.282m	26.260ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.952m	62.473ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.367m	50.354ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.216m	465.320us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.216m	465.320us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.216m	465.320us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.282m	26.260ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.880s	544.279us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.952m	62.473ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.880s	544.279us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.880s	544.279us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.216m	465.320us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.880s	544.279us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.008m	2.288ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1037	1040	99.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.94	99.19	94.27	99.72	100.00	96.03	99.12	97.26

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_regwen has 1 failures.

    • 21.sram_ctrl_regwen.111178191117033793114665204834022766472945509916077173632962220016758916982485
      Line 128, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/21.sram_ctrl_regwen/latest/run.log

        UVM_FATAL @ 137644673190 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x3d1eb511
        UVM_INFO @ 137644673190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_executable has 1 failures.

    • 35.sram_ctrl_executable.106295399435728799849276767573819913168915938324264351121041809254123314781220
      Line 119, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/35.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 158138555917 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x9f066695
        UVM_INFO @ 158138555917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_multiple_keys has 1 failures.

    • 48.sram_ctrl_multiple_keys.9112339247324094079289438590376979178782604942722389681620737008629319313555
      Line 87, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sram_ctrl_main-sim-vcs/48.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 16611604493 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x9eea824
        UVM_INFO @ 16611604493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.20_08.06.47
• 2024.08.19_08.20.14
• 2024.08.18_08.46.50
• 2024.08.17_07.27.33
• 2024.08.16_08.45.49
• 2024.08.15_05.42.57
• 2024.08.14_08.47.13