SRAM_CTRL/MAIN Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.018m	962.204us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.600s	50.235us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.610s	13.716us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.350s	520.921us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.600s	15.104us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.680s	6.841ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.610s	13.716us	20	20	100.00
		sram_ctrl_csr_aliasing	0.600s	15.104us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.743m	345.214ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.525m	11.016ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	16.931m	48.013ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.452m	26.326ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	39.655m	194.828ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	16.604m	18.575ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.508m	55.276ms	50	50	100.00
V2	executable	sram_ctrl_executable	17.983m	120.641ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.014m	6.837ms	49	50	98.00
		sram_ctrl_partial_access_b2b	11.446m	31.030ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.079m	3.178ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.006m	2.789ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	16.118m	82.338ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.770s	3.734ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.958h	2.060s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.610s	25.964us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.610s	1.035ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.610s	1.035ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.600s	50.235us	5	5	100.00
		sram_ctrl_csr_rw	0.610s	13.716us	20	20	100.00
		sram_ctrl_csr_aliasing	0.600s	15.104us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.770s	31.906us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.600s	50.235us	5	5	100.00
		sram_ctrl_csr_rw	0.610s	13.716us	20	20	100.00
		sram_ctrl_csr_aliasing	0.600s	15.104us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.770s	31.906us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.426m	117.331ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.870s	462.385us	5	5	100.00
		sram_ctrl_tl_intg_err	2.410s	353.776us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.870s	462.385us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.410s	353.776us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	16.118m	82.338ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.610s	13.716us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	17.983m	120.641ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	17.983m	120.641ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	17.983m	120.641ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.508m	55.276ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.426m	117.331ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.018m	962.204us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.018m	962.204us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.018m	962.204us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	17.983m	120.641ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.870s	462.385us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.508m	55.276ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.870s	462.385us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.870s	462.385us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.018m	962.204us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.870s	462.385us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.124m	2.894ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1037	1040	99.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 16.sram_ctrl_bijection.94166325285382330777146384769861635076987797804013345666991884276243087344579
      Line 83, in log /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 37.sram_ctrl_stress_all_with_rand_reset.106277728560623053353940286040233504432665531392737536204851315722966319086742
      Line 123, in log /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 27287446467 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x842b3a78
        UVM_INFO @ 27287446467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_partial_access has 1 failures.

    • 45.sram_ctrl_partial_access.21179261760617826870340881580650064284739296141294889175240397428519317356440
      Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access/latest/run.log

        UVM_FATAL @ 16644571697 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xe2f20536
        UVM_INFO @ 16644571697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.22_14.23.58
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