SRAM_CTRL/MAIN Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.243m	984.033us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.180s	23.490us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.110s	16.203us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.540s	119.019us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.180s	15.118us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	8.470s	475.149us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.110s	16.203us	20	20	100.00
		sram_ctrl_csr_aliasing	1.180s	15.118us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.209m	106.507ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.721m	64.550ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	37.685m	90.663ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	11.385m	6.287ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	56.000m	150.974ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	32.652m	103.504ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.222m	33.393ms	50	50	100.00
V2	executable	sram_ctrl_executable	36.521m	28.226ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.431m	1.999ms	50	50	100.00
		sram_ctrl_partial_access_b2b	13.287m	44.530ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.184m	6.347ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.326m	794.890us	50	50	100.00
V2	regwen	sram_ctrl_regwen	36.193m	74.968ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	10.520s	6.728ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.867h	349.599ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.100s	26.975us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	7.460s	263.513us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	7.460s	263.513us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.180s	23.490us	5	5	100.00
		sram_ctrl_csr_rw	1.110s	16.203us	20	20	100.00
		sram_ctrl_csr_aliasing	1.180s	15.118us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.360s	91.277us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.180s	23.490us	5	5	100.00
		sram_ctrl_csr_rw	1.110s	16.203us	20	20	100.00
		sram_ctrl_csr_aliasing	1.180s	15.118us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.360s	91.277us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.827m	29.399ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.160s	791.424us	5	5	100.00
		sram_ctrl_tl_intg_err	4.150s	229.959us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.160s	791.424us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.150s	229.959us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	36.193m	74.968ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.110s	16.203us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	36.521m	28.226ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	36.521m	28.226ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	36.521m	28.226ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.222m	33.393ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.827m	29.399ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.243m	984.033us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.243m	984.033us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.243m	984.033us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	36.521m	28.226ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.160s	791.424us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.222m	33.393ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.160s	791.424us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.160s	791.424us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.243m	984.033us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.160s	791.424us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.404m	11.000ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1037	1040	99.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test sram_ctrl_bijection has 2 failures.

    • 8.sram_ctrl_bijection.21345738410847814614296235877520405111226453308758751793842348628632637737659
      Line 83, in log /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/8.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 39.sram_ctrl_bijection.17539381322452980566247470466543529697773257852444558714416787438429944060196
      Line 83, in log /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/39.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_regwen has 1 failures.

    • 34.sram_ctrl_regwen.88818517844024798152436481913310480594207139782628250295434478037804798270743
      Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/34.sram_ctrl_regwen/latest/run.log

        UVM_FATAL @ 23208001886 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xd7dabfb4
        UVM_INFO @ 23208001886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.24_20.22.04
• 2024.08.22_14.23.58
• 2024.08.20_08.06.47
• 2024.08.19_08.20.14
• 2024.08.18_08.46.50
• 2024.08.17_07.27.33
• 2024.08.16_08.45.49