SRAM_CTRL/MAIN Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.826m	5.425ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.090s	15.444us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.060s	190.983us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.870s	1.468ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.140s	17.777us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	9.240s	2.369ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.060s	190.983us	20	20	100.00
		sram_ctrl_csr_aliasing	1.140s	17.777us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.659m	21.336ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.908m	48.560ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	26.379m	69.545ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	10.058m	6.495ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	54.414m	690.532ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	31.160m	44.501ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.326m	140.743ms	50	50	100.00
V2	executable	sram_ctrl_executable	31.332m	294.286ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	1.936m	1.295ms	50	50	100.00
		sram_ctrl_partial_access_b2b	13.744m	41.203ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.130m	1.666ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.871m	825.364us	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.319m	32.796ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.360s	1.401ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.322h	1.691s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.100s	62.294us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	7.240s	134.842us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	7.240s	134.842us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.090s	15.444us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	190.983us	20	20	100.00
		sram_ctrl_csr_aliasing	1.140s	17.777us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.280s	251.420us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.090s	15.444us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	190.983us	20	20	100.00
		sram_ctrl_csr_aliasing	1.140s	17.777us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.280s	251.420us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.907m	29.430ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.520s	488.461us	5	5	100.00
		sram_ctrl_tl_intg_err	5.520s	2.219ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.520s	488.461us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	5.520s	2.219ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.319m	32.796ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.060s	190.983us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	31.332m	294.286ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	31.332m	294.286ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	31.332m	294.286ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.326m	140.743ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.907m	29.430ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.826m	5.425ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.826m	5.425ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.826m	5.425ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	31.332m	294.286ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.520s	488.461us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.326m	140.743ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.520s	488.461us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.520s	488.461us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.826m	5.425ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.520s	488.461us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.009m	2.040ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1036	1040	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 30.sram_ctrl_bijection.75610010714701261710402250461299337772243437217789592055834651103889581809426
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 34.sram_ctrl_executable.43096598865745636710233720869723730927107491174475218469341417167590006369205
    Line 105, in log /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 99668693609 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x5d76e344
  UVM_INFO @ 99668693609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 40.sram_ctrl_stress_all_with_rand_reset.80005233467960048580119417174719222761697047874806860322935544051615443039858
    Line 108, in log /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12210305216 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12210305216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 46.sram_ctrl_multiple_keys.9134006411867436683632282240481058810658431644002941394054663191496569662582
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 20994865643 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xd8c364b0
  UVM_INFO @ 20994865643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `4674f625b3`