SRAM_CTRL/MAIN Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.931m	12.043ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.120s	45.011us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.090s	14.208us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.260s	469.875us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.030s	63.883us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	8.170s	4.951ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.090s	14.208us	20	20	100.00
		sram_ctrl_csr_aliasing	1.030s	63.883us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.655m	295.368ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.022m	45.779ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	25.655m	58.045ms	48	50	96.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	9.482m	5.277ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	51.180m	411.005ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	28.389m	41.159ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.257m	67.089ms	50	50	100.00
V2	executable	sram_ctrl_executable	21.995m	21.882ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.035m	548.977us	49	50	98.00
		sram_ctrl_partial_access_b2b	13.918m	48.266ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.899m	798.725us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.939m	2.904ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.481m	22.932ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	9.820s	5.599ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.239h	1.205s	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	1.080s	31.658us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	7.290s	506.277us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	7.290s	506.277us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.120s	45.011us	5	5	100.00
		sram_ctrl_csr_rw	1.090s	14.208us	20	20	100.00
		sram_ctrl_csr_aliasing	1.030s	63.883us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.140s	79.398us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.120s	45.011us	5	5	100.00
		sram_ctrl_csr_rw	1.090s	14.208us	20	20	100.00
		sram_ctrl_csr_aliasing	1.030s	63.883us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.140s	79.398us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.490m	7.358ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.090s	357.318us	5	5	100.00
		sram_ctrl_tl_intg_err	5.010s	580.746us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.090s	357.318us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	5.010s	580.746us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.481m	22.932ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.090s	14.208us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	21.995m	21.882ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	21.995m	21.882ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	21.995m	21.882ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.257m	67.089ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.490m	7.358ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.931m	12.043ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.931m	12.043ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.931m	12.043ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	21.995m	21.882ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.090s	357.318us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.257m	67.089ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.090s	357.318us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.090s	357.318us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.931m	12.043ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.090s	357.318us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.065m	4.752ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1032	1040	99.23

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.94	99.19	94.27	99.72	100.00	96.03	99.12	97.26

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_multiple_keys has 2 failures.
  - 2.sram_ctrl_multiple_keys.23130496795276807189142560811013759520017790066733197114813485998821809512161
    Line 117, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 155430212608 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x46dd5bad
  UVM_INFO @ 155430212608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.sram_ctrl_multiple_keys.40732202295234465060533521495745689686265867328792067492999238771034105004099
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 72418829107 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xc07db73c
  UVM_INFO @ 72418829107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_stress_all has 2 failures.
  - 14.sram_ctrl_stress_all.61132359587052361804473671227911935670830849413213013929313663781975090345743
    Line 146, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 184195055912 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xc4d05ee0
  UVM_INFO @ 184195055912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.sram_ctrl_stress_all.8566077085705891891103698372306291128159201772572663643106194937896128945977
    Line 101, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 4101399398046 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xb2eb1975
  UVM_INFO @ 4101399398046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 41.sram_ctrl_bijection.5306556010039874625207598207804212913362220853386771057336973697718224255517
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.sram_ctrl_bijection.19003858441965539782497859510131251945376304622902318352365386818315741626781
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 0.sram_ctrl_stress_all_with_rand_reset.33523953998535438581279974542883660777549654723022351785423281159319940428847
    Line 102, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2589781322 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2589781322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_partial_access has 1 failures.
  - 21.sram_ctrl_partial_access.114806510543041222772859831660839778327126523809932994223128325790906204920427
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access/latest/run.log
```
  UVM_FATAL @ 21004335826 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xedbf21dc
  UVM_INFO @ 21004335826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a861deb3de`